Home
last modified time | relevance | path

Searched refs:rtw_write32_mask (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/net/wireless/realtek/rtw88/
A Drtw8822c.c1252 rtw_write32_mask(rtwdev, REG_3WIRE2, in rtw8822c_txgapk_bb_dpk()
1359 rtw_write32_mask(rtwdev, REG_3WIRE2, in rtw8822c_txgapk_bb_dpk_restore()
1540 rtw_write32_mask(rtwdev, in rtw8822c_txgapk_calculate_offset()
1562 rtw_write32_mask(rtwdev, in rtw8822c_txgapk_calculate_offset()
1583 rtw_write32_mask(rtwdev, in rtw8822c_txgapk_calculate_offset()
1586 rtw_write32_mask(rtwdev, in rtw8822c_txgapk_calculate_offset()
1589 rtw_write32_mask(rtwdev, in rtw8822c_txgapk_calculate_offset()
1731 rtw_write32_mask(rtwdev, in rtw8822c_txgapk_save_all_tx_gain_table()
1756 rtw_write32_mask(rtwdev, in rtw8822c_txgapk_save_all_tx_gain_table()
4372 rtw_write32_mask(rtwdev, in rtw8822c_phy_cck_pd_set_reg()
[all …]
A Drtw8822b.c72 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); in rtw8822b_phy_rfe_init()
75 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); in rtw8822b_phy_rfe_init()
79 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); in rtw8822b_phy_rfe_init()
153 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); in rtw8822b_phy_set_param()
466 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); in rtw8822b_set_channel_cca()
561 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); in rtw8822b_toggle_igi()
563 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); in rtw8822b_toggle_igi()
566 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, in rtw8822b_toggle_igi()
636 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); in rtw8822b_set_channel_bb()
783 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); in rtw8822b_config_trx_mode()
[all …]
A Drtw8821c.c333 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
334 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
339 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
340 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
346 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
368 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, in rtw8821c_set_channel_bb()
370 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, in rtw8821c_set_channel_bb()
372 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, in rtw8821c_set_channel_bb()
438 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
447 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
[all …]
A Drtw8723d.c156 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, in rtw8723d_phy_set_param()
201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_phy_set_param()
509 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, in rtw8723d_set_channel_bb()
1140 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, in rtw8723d_iqk_fill_s1_matrix()
1142 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, in rtw8723d_iqk_fill_s1_matrix()
1149 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, in rtw8723d_iqk_fill_s1_matrix()
1151 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, in rtw8723d_iqk_fill_s1_matrix()
1163 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X, in rtw8723d_iqk_fill_s1_matrix()
1526 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, in rtw8723d_phy_cck_pd_set()
1817 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, in rtw8723d_pwrtrack_set_cck_pwr()
[all …]
A Defuse.c16 rtw_write32_mask(rtwdev, REG_LDO_EFUSE_CTRL, BIT_MASK_EFUSE_BANK_SEL, in switch_efuse_bank()
130 rtw_write32_mask(rtwdev, REG_EFUSE_CTRL, 0x3ff00, addr); in rtw_read8_physical_efuse()
A Drtw8822b.h104 rtw_write32_mask(rtwdev, addr, mask, data); in _rtw_write32s_mask()
105 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
A Drtw8821c.h83 rtw_write32_mask(rtwdev, addr, mask, data); in _rtw_write32s_mask()
84 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
A Dmac80211.c335 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_TXOP_LMT, params->txop); in __rtw_conf_tx()
336 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_CWMAX, ecw_max); in __rtw_conf_tx()
337 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_CWMIN, ecw_min); in __rtw_conf_tx()
338 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_AIFS, aifs); in __rtw_conf_tx()
A Dphy.c127 rtw_write32_mask(rtwdev, in rtw_phy_set_edcca_th()
131 rtw_write32_mask(rtwdev, in rtw_phy_set_edcca_th()
235 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1); in rtw_phy_dig_write()
241 rtw_write32_mask(rtwdev, addr, mask, igi); in rtw_phy_dig_write()
1027 rtw_write32_mask(rtwdev, direct_addr, mask, data); in rtw_phy_write_rf_reg()
1755 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1); in rtw_load_rfk_table()
1756 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1); in rtw_load_rfk_table()
1757 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1); in rtw_load_rfk_table()
1758 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1); in rtw_load_rfk_table()
1759 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0); in rtw_load_rfk_table()
A Dhci.h230 rtw_write32_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) in rtw_write32_mask() function
A Dbf.c371 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE, in rtw_bf_phy_init()
A Dmain.c799 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); in rtw_vif_port_config()
804 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); in rtw_vif_port_config()
A Dpci.c1321 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1); in rtw_mdio_write()
1465 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG, in rtw_pci_interface_cfg()

Completed in 49 milliseconds