Home
last modified time | relevance | path

Searched refs:simd (Results 1 – 21 of 21) sorted by relevance

/linux/crypto/
A Dsimd.c237 struct simd_skcipher_alg *simd; in simd_register_skciphers_compat() local
249 simd = simd_skcipher_create_compat(algname, drvname, basename); in simd_register_skciphers_compat()
250 err = PTR_ERR(simd); in simd_register_skciphers_compat()
251 if (IS_ERR(simd)) in simd_register_skciphers_compat()
253 simd_algs[i] = simd; in simd_register_skciphers_compat()
484 struct simd_aead_alg *simd; in simd_register_aeads_compat() local
496 simd = simd_aead_create_compat(algname, drvname, basename); in simd_register_aeads_compat()
497 err = PTR_ERR(simd); in simd_register_aeads_compat()
498 if (IS_ERR(simd)) in simd_register_aeads_compat()
500 simd_algs[i] = simd; in simd_register_aeads_compat()
A DMakefile201 crypto_simd-y := simd.o
A D.testmgr.o.cmd1010 include/crypto/internal/simd.h \
/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
437 for (simd = 0; simd < SIMD_ID_MAX; simd++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
467 for (simd = 0; simd < SIMD_ID_MAX; simd++) in gfx_v9_4_2_wait_for_waves_assigned()
1830 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1840 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1851 simd = i / cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1858 wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_2_log_cu_timeout_status()
1860 wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_2_log_cu_timeout_status()
1862 wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_4_2_log_cu_timeout_status()
[all …]
A Dgfx_v6_0.c2987 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2993 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2999 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
3017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v6_0_read_wave_data()
3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v6_0_read_wave_data()
3029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v6_0_read_wave_data()
3030 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v6_0_read_wave_data()
[all …]
A Damdgpu_gfx.h225 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
227 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
230 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
A Dgfx_v7_0.c4162 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4168 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4174 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
4187 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4188 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4189 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4192 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v7_0_read_wave_data()
4198 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v7_0_read_wave_data()
4204 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v7_0_read_wave_data()
4205 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v7_0_read_wave_data()
[all …]
A Damdgpu_debugfs.c891 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
902 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; in amdgpu_debugfs_wave_read()
922 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
983 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
994 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; in amdgpu_debugfs_gpr_read()
1016 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1019 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
A Dgfx_v8_0.c5239 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5245 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
5251 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
5264 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5265 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5266 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5269 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v8_0_read_wave_data()
5275 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v8_0_read_wave_data()
5281 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v8_0_read_wave_data()
5282 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v8_0_read_wave_data()
[all …]
A Dgfx_v9_0.c2064 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2070 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2076 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
2089 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
2090 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
2091 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
2094 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v9_0_read_wave_data()
2102 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v9_0_read_wave_data()
2103 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v9_0_read_wave_data()
2111 adev, simd, wave, 0, in gfx_v9_0_read_wave_sgprs()
[all …]
A Dgfx_v10_0.c4578 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint… in gfx_v10_0_read_wave_data() argument
4583 WARN_ON(simd != 0); in gfx_v10_0_read_wave_data()
4605 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, in gfx_v10_0_read_wave_sgprs() argument
4609 WARN_ON(simd != 0); in gfx_v10_0_read_wave_sgprs()
4616 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, in gfx_v10_0_read_wave_vgprs() argument
/linux/arch/arm/crypto/
A Daes-neonbs-glue.c528 struct simd_skcipher_alg *simd; in aes_init() local
549 simd = simd_skcipher_create_compat(algname, drvname, basename); in aes_init()
550 err = PTR_ERR(simd); in aes_init()
551 if (IS_ERR(simd)) in aes_init()
554 aes_simd_algs[i] = simd; in aes_init()
A Daes-ce-glue.c696 struct simd_skcipher_alg *simd; in aes_init() local
714 simd = simd_skcipher_create_compat(algname, drvname, basename); in aes_init()
715 err = PTR_ERR(simd); in aes_init()
716 if (IS_ERR(simd)) in aes_init()
719 aes_simd_algs[i] = simd; in aes_init()
/linux/include/asm-generic/
A DKbuild52 mandatory-y += simd.h
/linux/arch/arm64/crypto/
A D.sha256-glue.o.cmd368 arch/arm64/include/asm/simd.h \
602 include/crypto/internal/simd.h \
A D.aes-ce-glue.o.cmd368 arch/arm64/include/asm/simd.h \
602 include/crypto/internal/simd.h \
A D.sha1-ce-glue.o.cmd368 arch/arm64/include/asm/simd.h \
605 include/crypto/internal/simd.h \
A D.sha2-ce-glue.o.cmd368 arch/arm64/include/asm/simd.h \
605 include/crypto/internal/simd.h \
A D.aes-glue-ce.o.cmd369 arch/arm64/include/asm/simd.h \
609 include/crypto/internal/simd.h \
A D.ghash-ce-glue.o.cmd368 arch/arm64/include/asm/simd.h \
610 include/crypto/internal/simd.h \
/linux/arch/arm64/kernel/
A D.fpsimd.o.cmd1099 arch/arm64/include/asm/simd.h \

Completed in 96 milliseconds