| /linux/arch/arm/include/asm/mach/ |
| A D | pci.h | 27 u8 (*swizzle)(struct pci_dev *dev, u8 *pin); member
44 u8 (*swizzle)(struct pci_dev *, u8 *); member
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| /linux/drivers/gpu/drm/i915/gem/selftests/ |
| A D | i915_gem_mman.c | 26 unsigned int swizzle; member
64 switch (tile->swizzle) { in tiled_offset()
342 tile.swizzle = I915_BIT_6_SWIZZLE_NONE; in igt_partial_tiling()
367 tile.swizzle = i915->ggtt.bit_6_swizzle_x; in igt_partial_tiling()
370 tile.swizzle = i915->ggtt.bit_6_swizzle_y; in igt_partial_tiling()
375 if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 || in igt_partial_tiling()
376 tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17) in igt_partial_tiling()
483 tile.swizzle = I915_BIT_6_SWIZZLE_NONE; in igt_smoke_tiling()
487 tile.swizzle = i915->ggtt.bit_6_swizzle_x; in igt_smoke_tiling()
490 tile.swizzle = i915->ggtt.bit_6_swizzle_y; in igt_smoke_tiling()
[all …]
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| A D | i915_gem_client_blt.c | 209 unsigned int swizzle; in tiled_offset() local
223 swizzle = gt->ggtt->bit_6_swizzle_x; in tiled_offset()
233 swizzle = gt->ggtt->bit_6_swizzle_y; in tiled_offset()
236 switch (swizzle) { in tiled_offset()
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| /linux/arch/arm/kernel/ |
| A D | bios32.c | 367 if (sys->swizzle) in pcibios_swizzle()
368 slot = sys->swizzle(dev, pin); in pcibios_swizzle()
445 sys->swizzle = hw->swizzle; in pcibios_init_hw()
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| /linux/arch/arm/mach-footbridge/ |
| A D | cats-pci.c | 48 .swizzle = cats_no_swizzle,
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| /linux/arch/arm64/boot/dts/qcom/ |
| A D | sc7180-trogdor-lazor-r0.dts | 32 * that means we no longer need the swizzle.
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_display.c | 686 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier() local
687 bool has_xor = swizzle >= 16; in convert_tiling_flags_to_modifier()
697 switch (swizzle >> 2) { in convert_tiling_flags_to_modifier()
722 switch (swizzle & 3) { in convert_tiling_flags_to_modifier()
970 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); in amdgpu_display_verify_sizes() local
972 switch ((swizzle & ~3) + 1) { in amdgpu_display_verify_sizes()
987 "Swizzle mode with unknown block size: %d\n", swizzle); in amdgpu_display_verify_sizes()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_trace.h | 416 __field(int, swizzle)
448 __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
482 __entry->swizzle,
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_debug.c | 170 plane_state->tiling_info.gfx9.swizzle); in pre_surface_trace()
256 update->plane_info->tiling_info.gfx9.swizzle); in update_surface_trace()
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| A D | dc_hw_sequencer.c | 418 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dchubbub.h | 132 enum swizzle_mode_values swizzle,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_hubbub.c | 138 enum swizzle_mode_values swizzle, in hubbub3_dcc_support_swizzle() argument
147 switch (swizzle) { in hubbub3_dcc_support_swizzle()
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| A D | dcn30_hubbub.h | 114 enum swizzle_mode_values swizzle,
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| A D | dcn30_hubp.c | 335 SW_MODE, info->gfx9.swizzle, in hubp3_program_tiling()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_hubbub.h | 108 enum swizzle_mode_values swizzle,
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| A D | dcn20_hubbub.c | 57 enum swizzle_mode_values swizzle, in hubbub2_dcc_support_swizzle() argument
66 switch (swizzle) { in hubbub2_dcc_support_swizzle()
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| A D | dcn20_resource.c | 1824 enum swizzle_mode_values swizzle, in swizzle_to_dml_params() argument
1827 switch (swizzle) { in swizzle_to_dml_params()
2342 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
2343 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
3371 enum swizzle_mode_values swizzle = DC_SW_LINEAR; in dcn20_patch_unknown_plane_state() local
3374 swizzle = DC_SW_64KB_D; in dcn20_patch_unknown_plane_state()
3376 swizzle = DC_SW_64KB_S; in dcn20_patch_unknown_plane_state()
3378 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn20_patch_unknown_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_resource.c | 1272 enum swizzle_mode_values swizzle = DC_SW_LINEAR; in dcn10_patch_unknown_plane_state() local
1275 swizzle = DC_SW_64KB_D; in dcn10_patch_unknown_plane_state()
1277 swizzle = DC_SW_64KB_S; in dcn10_patch_unknown_plane_state()
1279 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
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| A D | dcn10_hubbub.c | 713 enum swizzle_mode_values swizzle, in hubbub1_dcc_support_swizzle() argument
721 switch (swizzle) { in hubbub1_dcc_support_swizzle()
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| A D | dcn10_hubp.c | 157 SW_MODE, info->gfx9.swizzle, in hubp1_program_tiling()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| A D | com.fuc | 416 // Calculates the hw swizzle mask and adjusts the surface's xcnt to match
419 // zero out a chunk of the stack to store the swizzle into
435 // convert FORMAT swizzle mask to hw swizzle mask
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| /linux/drivers/gpu/drm/i915/ |
| A D | i915_debugfs.c | 362 static const char *swizzle_string(unsigned swizzle) in swizzle_string() argument
364 switch (swizzle) { in swizzle_string()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_hw_types.h | 371 enum swizzle_mode_values swizzle; member
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| /linux/drivers/gpu/drm/amd/display/dc/calcs/ |
| A D | dcn_calcs.c | 339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle); in pipe_ctx_to_e2e_pipe_params()
1029 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_mem_input.c | 437 GRPH_SW_MODE, info->gfx9.swizzle, in program_tiling()
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