Searched refs:tg_inst (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_hwseq.c | 177 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
205 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
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| A D | dce_stream_encoder.c | 1508 int tg_inst, bool enable) in setup_stereo_sync() argument
1511 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1517 int tg_inst) in dig_connect_to_otg() argument
1521 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1527 uint32_t tg_inst = 0; in dig_source_otg() local
1530 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1532 return tg_inst; in dig_source_otg()
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| A D | dce_hwseq.h | 1207 unsigned int tg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/virtual/ |
| A D | virtual_stream_encoder.c | 95 int tg_inst) in virtual_dig_connect_to_otg() argument
100 int tg_inst, in virtual_setup_stereo_sync() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_stream_encoder.c | 1484 int tg_inst, bool enable) in enc1_setup_stereo_sync() argument
1487 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync()
1493 int tg_inst) in enc1_dig_connect_to_otg() argument
1497 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in enc1_dig_connect_to_otg()
1503 uint32_t tg_inst = 0; in enc1_dig_source_otg() local
1506 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in enc1_dig_source_otg()
1508 return tg_inst; in enc1_dig_source_otg()
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| A D | dcn10_stream_encoder.h | 640 int tg_inst, bool enable);
672 int tg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | stream_encoder.h | 201 int tg_inst,
209 int tg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 2013 unsigned int i, inst, tg_inst = 0; in acquire_resource_from_hw_enabled_state() local
2036 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
2039 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state()
2043 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; in acquire_resource_from_hw_enabled_state()
2044 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; in acquire_resource_from_hw_enabled_state()
2045 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; in acquire_resource_from_hw_enabled_state()
2047 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; in acquire_resource_from_hw_enabled_state()
2048 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; in acquire_resource_from_hw_enabled_state()
2050 if (pool->dpps[tg_inst]) { in acquire_resource_from_hw_enabled_state()
2070 pipe_ctx->pipe_idx = tg_inst; in acquire_resource_from_hw_enabled_state()
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| A D | dc.c | 1151 unsigned int enc_inst, tg_inst = 0; in disable_vbios_mode_if_required() local
1158 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( in disable_vbios_mode_if_required()
1166 tg_inst, &pix_clk_100hz); in disable_vbios_mode_if_required()
1483 unsigned int i, enc_inst, tg_inst = 0; in dc_validate_seamless_boot_timing() local
1504 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( in dc_validate_seamless_boot_timing()
1514 if (tg_inst >= dc->res_pool->timing_generator_count) in dc_validate_seamless_boot_timing()
1517 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_seamless_boot_timing()
1570 tg_inst, &pix_clk_100hz); in dc_validate_seamless_boot_timing()
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| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| A D | dmub_cmd.h | 2331 uint32_t tg_inst; member
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