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Searched refs:tile (Results 1 – 25 of 87) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dnv20.c35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
51 tile->zcomp |= tile->tag->offset; in nv20_fb_tile_comp()
54 tile->zcomp |= 0x08000000; in nv20_fb_tile_comp()
62 tile->addr = 0; in nv20_fb_tile_fini()
63 tile->limit = 0; in nv20_fb_tile_fini()
64 tile->pitch = 0; in nv20_fb_tile_fini()
65 tile->zcomp = 0; in nv20_fb_tile_fini()
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A Dnv30.c35 tile->addr = (0 << 4); in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
57 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv30_fb_tile_comp()
58 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12; in nv30_fb_tile_comp()
60 tile->zcomp |= 0x10000000; in nv30_fb_tile_comp()
121 .tile.regions = 8,
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A Dnv10.c33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
59 .tile.regions = 8,
60 .tile.init = nv10_fb_tile_init,
61 .tile.fini = nv10_fb_tile_fini,
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A Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
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A Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
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A Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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A Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
61 .tile.init = nv44_fb_tile_init,
62 .tile.fini = nv20_fb_tile_fini,
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A Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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A Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
168 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
169 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
205 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
206 fb->func->tile.fini(fb, i, &fb->tile.region[i]); in nvkm_fb_dtor()
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A Dnv47.c33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
A Dnv49.c33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
A Dnv1a.c31 .tile.regions = 8,
32 .tile.init = nv10_fb_tile_init,
33 .tile.fini = nv10_fb_tile_fini,
34 .tile.prog = nv10_fb_tile_prog,
A Dnv4e.c32 .tile.regions = 12,
33 .tile.init = nv46_fb_tile_init,
34 .tile.fini = nv20_fb_tile_fini,
35 .tile.prog = nv44_fb_tile_prog,
/linux/drivers/gpu/drm/i915/gem/selftests/
A Di915_gem_mman.c42 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; in tiled_offset()
83 const struct tile *tile, in check_partial_mapping() argument
100 tile->tiling, tile->stride, err); in check_partial_mapping()
173 const struct tile *tile, in check_partial_mappings() argument
185 tile->tiling, tile->stride, err); in check_partial_mappings()
336 struct tile tile; in igt_partial_tiling() local
354 struct tile tile; in igt_partial_tiling() local
382 tile.stride = tile.width * pitch; in igt_partial_tiling()
410 tile.stride = tile.width * pitch; in igt_partial_tiling()
473 struct tile tile; in igt_smoke_tiling() local
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dnv44.c44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
61 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
63 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
66 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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A Dnv40.c189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
214 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
215 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
216 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
219 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
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A Dnv20.c149 nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv20_gr_tile() argument
159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile()
160 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile()
161 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile()
164 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile()
166 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile()
168 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr); in nv20_gr_tile()
171 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv20_gr_tile()
173 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); in nv20_gr_tile()
350 .tile = nv20_gr_tile,
A Dbase.c65 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) in nvkm_gr_tile() argument
68 if (gr->func->tile) in nvkm_gr_tile()
69 gr->func->tile(gr, region, tile); in nvkm_gr_tile()
170 .tile = nvkm_gr_tile,
/linux/drivers/gpu/ipu-v3/
A Dipu-image-convert.c878 tile = &image->tile[i]; in calc_tile_dimensions()
884 tile->stride = tile->width; in calc_tile_dimensions()
885 tile->rot_stride = tile->height; in calc_tile_dimensions()
898 tile->width, tile->height, tile->left, tile->top); in calc_tile_dimensions()
1009 top = image->tile[tile].top; in calc_tile_offsets_planar()
1030 image->tile[tile].offset = y_off; in calc_tile_offsets_planar()
1031 image->tile[tile].u_off = u_off; in calc_tile_offsets_planar()
1073 image->tile[tile].u_off = 0; in calc_tile_offsets_packed()
1074 image->tile[tile++].v_off = 0; in calc_tile_offsets_packed()
1425 s_image->tile[tile].width, in convert_start()
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/linux/drivers/gpu/drm/nouveau/
A Dnouveau_bo.c61 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
65 if (tile->pitch) in nv10_bo_update_tile_region()
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region() local
82 if (!tile->used && in nv10_bo_get_tile_region()
83 (!tile->fence || nouveau_fence_done(tile->fence))) in nv10_bo_get_tile_region()
84 tile->used = true; in nv10_bo_get_tile_region()
86 tile = NULL; in nv10_bo_get_tile_region()
89 return tile; in nv10_bo_get_tile_region()
98 if (tile) { in nv10_bo_put_tile_region()
119 found = tile; in nv10_bo_set_tiling()
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/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v7_0.c1030 uint32_t *tile, *macrotile; in gfx_v7_0_tiling_mode_table_init() local
1032 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1049 tile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1055 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1059 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1063 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1067 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1071 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1075 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1083 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v7_0_tiling_mode_table_init()
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/linux/Documentation/devicetree/bindings/arm/
A Darm,vexpress-juno.yaml22 The motherboard and each core tile should be described by a separate Device
23 Tree source file, with the tile's description including the motherboard file
33 The root node indicates the CPU SoC on the core tile, and this
35 string shall match the name given in the core tile's technical reference
37 further subvariants are released of the core tile, even more fine-granular
46 in MPCore configuration in a test chip on the core tile. See ARM
52 in a test chip on the core tile. It is intended to evaluate NEON, FPU
58 cores in a MPCore configuration in a test chip on the core tile. See
72 in a test chip on the core tile. See ARM DDI 0503I.
77 cores in a test chip on the core tile. See ARM DDI 0498D.
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/linux/drivers/hid/
A Dhid-picolcd_fb.c91 int chip, int tile) in picolcd_fb_send_tile() argument
114 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
127 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
142 int chip, int tile) in picolcd_fb_update_tile() argument
146 u8 *vdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_update_tile()
150 const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32; in picolcd_fb_update_tile()
158 const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8; in picolcd_fb_update_tile()
227 int chip, tile, n; in picolcd_fb_update() local
248 for (tile = 0; tile < 8; tile++) { in picolcd_fb_update()
251 fbdata->bpp, chip, tile)) in picolcd_fb_update()
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