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Searched refs:timer_of_base (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/clocksource/
A Dtimer-npcm7xx.c61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
63 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
75 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
88 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_periodic()
158 timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0); in npcm7xx_clockevents_init()
161 timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR); in npcm7xx_clockevents_init()
174 timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); in npcm7xx_clocksource_init()
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A Dtimer-sun4i.c89 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_shutdown()
98 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_set_oneshot()
108 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_set_periodic()
110 sun4i_clkevt_time_start(timer_of_base(to), 0, true); in sun4i_clkevt_set_periodic()
120 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_next_event()
137 sun4i_timer_clear_interrupt(timer_of_base(to)); in sun4i_timer_interrupt()
181 timer_of_base(&to) + TIMER_CTL_REG(1)); in sun4i_timer_init()
203 timer_of_base(&to) + TIMER_CTL_REG(0)); in sun4i_timer_init()
206 sun4i_clkevt_time_stop(timer_of_base(&to), 0); in sun4i_timer_init()
209 sun4i_timer_clear_interrupt(timer_of_base(&to)); in sun4i_timer_init()
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A Dtimer-mediatek.c144 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + in mtk_gpt_clkevt_time_stop()
173 timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_clkevt_time_start()
222 timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_setup()
225 timer_of_base(to) + GPT_CLK_REG(timer)); in mtk_gpt_setup()
230 timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_setup()
238 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); in mtk_gpt_enable_irq()
241 writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG); in mtk_gpt_enable_irq()
243 val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); in mtk_gpt_enable_irq()
245 timer_of_base(to) + GPT_IRQ_EN_REG); in mtk_gpt_enable_irq()
260 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); in mtk_gpt_suspend()
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A Drenesas-ostm.c46 if (readb(timer_of_base(to) + OSTM_TE) & TE) { in ostm_timer_stop()
47 writeb(TT, timer_of_base(to) + OSTM_TT); in ostm_timer_stop()
54 while (readb(timer_of_base(to) + OSTM_TE) & TE) in ostm_timer_stop()
63 writel(0, timer_of_base(to) + OSTM_CMP); in ostm_init_clksrc()
64 writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL); in ostm_init_clksrc()
65 writeb(TS, timer_of_base(to) + OSTM_TS); in ostm_init_clksrc()
79 system_clock = timer_of_base(to) + OSTM_CNT; in ostm_init_sched_clock()
90 writel(delta, timer_of_base(to) + OSTM_CMP); in ostm_clock_event_next()
91 writeb(CTL_ONESHOT, timer_of_base(to) + OSTM_CTL); in ostm_clock_event_next()
92 writeb(TS, timer_of_base(to) + OSTM_TS); in ostm_clock_event_next()
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A Dtimer-sprd.c84 sprd_timer_disable(timer_of_base(to)); in sprd_timer_set_next_event()
85 sprd_timer_update_counter(timer_of_base(to), cycles); in sprd_timer_set_next_event()
86 sprd_timer_enable(timer_of_base(to), 0); in sprd_timer_set_next_event()
95 sprd_timer_disable(timer_of_base(to)); in sprd_timer_set_periodic()
106 sprd_timer_disable(timer_of_base(to)); in sprd_timer_shutdown()
115 sprd_timer_clear_interrupt(timer_of_base(to)); in sprd_timer_interrupt()
118 sprd_timer_disable(timer_of_base(to)); in sprd_timer_interrupt()
152 sprd_timer_enable_interrupt(timer_of_base(&to)); in sprd_timer_init()
165 return ~(u64)readl_relaxed(timer_of_base(&suspend_to) + in sprd_suspend_timer_read()
171 sprd_timer_update_counter(timer_of_base(&suspend_to), in sprd_suspend_timer_enable()
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A Dtimer-milbeaut.c55 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_timer_interrupt()
57 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_timer_interrupt()
71 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_start()
79 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_stop()
84 writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); in mlb_evt_timer_register_count()
129 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
130 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); in mlb_config_clock_source()
131 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); in mlb_config_clock_source()
133 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
139 writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_config_clock_event()
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A Dtimer-atcpit100.c127 val = readl(timer_of_base(to) + CH_EN); in atcpit100_clkevt_next_event()
129 writel(evt, timer_of_base(to) + CH0_REL); in atcpit100_clkevt_next_event()
130 writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); in atcpit100_clkevt_next_event()
140 atcpit100_clkevt_time_start(timer_of_base(to)); in atcpit100_clkevt_set_periodic()
148 atcpit100_clkevt_time_stop(timer_of_base(to)); in atcpit100_clkevt_shutdown()
157 writel(~0x0, timer_of_base(to) + CH0_REL); in atcpit100_clkevt_set_oneshot()
158 val = readl(timer_of_base(to) + CH_EN); in atcpit100_clkevt_set_oneshot()
159 writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); in atcpit100_clkevt_set_oneshot()
169 atcpit100_timer_clear_interrupt(timer_of_base(to)); in atcpit100_timer_interrupt()
207 return ~readl(timer_of_base(&to) + CH1_CNT); in atcpit100_timer_sched_read()
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A Dtimer-stm32.c101 writel_relaxed(0, timer_of_base(to) + TIM_DIER); in stm32_clock_event_disable()
132 next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; in stm32_clock_event_set_next_event()
133 writel_relaxed(next, timer_of_base(to) + TIM_CCR1); in stm32_clock_event_set_next_event()
134 now = readl_relaxed(timer_of_base(to) + TIM_CNT); in stm32_clock_event_set_next_event()
167 writel_relaxed(0, timer_of_base(to) + TIM_SR); in stm32_clock_event_handler()
192 writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); in stm32_timer_set_width()
194 width = readl_relaxed(timer_of_base(to) + TIM_ARR); in stm32_timer_set_width()
222 writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); in stm32_timer_set_prescaler()
223 writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); in stm32_timer_set_prescaler()
224 writel_relaxed(0, timer_of_base(to) + TIM_SR); in stm32_timer_set_prescaler()
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A Dtimer-gx6605s.c28 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_interrupt()
40 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_set_oneshot()
55 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_set_next_event()
69 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_shutdown()
98 base = timer_of_base(&to) + CLKSRC_OFFSET; in gx6605s_sched_clock_read()
151 gx6605s_clkevt_init(timer_of_base(&to)); in gx6605s_timer_init()
153 return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET); in gx6605s_timer_init()
A Dtimer-rda.c71 rda_ostimer_stop(timer_of_base(to)); in rda_ostimer_set_state_shutdown()
80 rda_ostimer_stop(timer_of_base(to)); in rda_ostimer_set_state_oneshot()
90 rda_ostimer_stop(timer_of_base(to)); in rda_ostimer_set_state_periodic()
94 rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy); in rda_ostimer_set_state_periodic()
109 rda_ostimer_start(timer_of_base(to), false, evt); in rda_ostimer_set_next_event()
121 timer_of_base(to) + RDA_TIMER_IRQ_CLR); in rda_ostimer_interrupt()
158 void __iomem *base = timer_of_base(&rda_ostimer_of); in rda_hwtimer_read()
A Dtimer-tegra.c57 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); in tegra_timer_set_next_event()
75 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); in tegra_timer_shutdown()
84 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); in tegra_timer_set_periodic()
96 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); in tegra_timer_isr()
106 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); in tegra_timer_suspend()
136 writel_relaxed(0, timer_of_base(to) + TIMER_PTV); in tegra_timer_setup()
137 writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); in tegra_timer_setup()
196 void __iomem *reg_base = timer_of_base(&suspend_rtc_to); in tegra_rtc_read_ms()
262 timer_reg_base = timer_of_base(to); in tegra_init_timer()
A Dtimer-of.h49 static inline void __iomem *timer_of_base(struct timer_of *to) in timer_of_base() function
A Dtimer-imx-sysctr.c140 sys_ctr_base = timer_of_base(&to_sysctr); in sysctr_timer_init()
A Dtimer-imx-tpm.c197 timer_base = timer_of_base(&to_tpm); in tpm_timer_init()

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