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Searched refs:ufshcd_writel (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/scsi/ufs/
A Dufshcd-crypto.c35 ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in ufshcd_program_key()
37 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]), in ufshcd_program_key()
41 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]), in ufshcd_program_key()
44 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]), in ufshcd_program_key()
A Dufs-mediatek.c187 ufshcd_writel(hba, 0, in ufs_mtk_hce_enable_notify()
250 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
253 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
305 ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL); in ufs_mtk_dbg_sel()
306 ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0); in ufs_mtk_dbg_sel()
307 ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1); in ufs_mtk_dbg_sel()
308 ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2); in ufs_mtk_dbg_sel()
309 ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3); in ufs_mtk_dbg_sel()
311 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); in ufs_mtk_dbg_sel()
1000 ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_mtk_auto_hibern8_disable()
A Dcdns-pltfrm.c134 ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV); in cdns_ufs_set_hclkdiv()
246 ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1); in cdns_ufs_m31_16nm_phy_initialization()
A Dufs-qcom.c350 ufshcd_writel(hba, in ufs_qcom_enable_hw_clk_gating()
447 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
509 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, in ufs_qcom_cfg_timers()
519 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), in ufs_qcom_cfg_timers()
1278 ufshcd_writel(hba, reg, REG_UFS_CFG1); in ufs_qcom_print_hw_debug_reg_all()
A Dufshcd-dwc.c44 ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV); in ufshcd_dwc_program_clk_div()
A Dufshcd.c736 ufshcd_writel(hba, ~(1 << pos), in ufshcd_utrl_clear()
848 ufshcd_writel(hba, INT_AGGR_ENABLE | in ufshcd_reset_intr_aggr()
885 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg()
887 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg()
902 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); in ufshcd_hba_start()
2424 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); in ufshcd_enable_intr()
2446 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); in ufshcd_disable_intr()
4462 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), in ufshcd_make_hba_operational()
4464 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), in ufshcd_make_hba_operational()
4466 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), in ufshcd_make_hba_operational()
[all …]
A Dufs-hisi.c230 ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); in ufs_hisi_link_startup_pre_change()
235 ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_hisi_link_startup_pre_change()
A Dufshcd.h1000 #define ufshcd_writel(hba, val, reg) \ macro
1019 ufshcd_writel(hba, tmp, reg); in ufshcd_rmwl()
A Dufshcd-pci.c95 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify()
A Dufs-exynos.c307 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); in exynosauto_ufs_post_pwr_change()

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