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Searched refs:vlv_dpio_write (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_dpio_phy.c690 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
769 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
786 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
834 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_phy_pre_pll_enable()
874 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_phy_pre_pll_enable()
911 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_phy_pre_encoder_enable()
937 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), in chv_phy_pre_encoder_enable()
945 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), in chv_phy_pre_encoder_enable()
1019 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), in vlv_set_phy_signal_level()
1045 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_phy_pre_pll_enable()
[all …]
A Dintel_dpll.c1498 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
1542 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); in vlv_prepare_pll()
1565 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
1568 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
1574 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
1577 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
1582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
1585 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
1664 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), in chv_prepare_pll()
1674 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), in chv_prepare_pll()
[all …]
A Dintel_display_power.c1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); in chv_dpio_cmn_power_well_enable()
1675 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); in chv_dpio_cmn_power_well_enable()
1684 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); in chv_dpio_cmn_power_well_enable()
/linux/drivers/gpu/drm/i915/
A Dvlv_sideband.h77 void vlv_dpio_write(struct drm_i915_private *i915,
A Dvlv_sideband.c245 void vlv_dpio_write(struct drm_i915_private *i915, in vlv_dpio_write() function

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