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Searched refs:vmw_write (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_ldu.c115 vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS, in vmw_ldu_commit_list()
122 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i); in vmw_ldu_commit_list()
123 vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i); in vmw_ldu_commit_list()
124 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x); in vmw_ldu_commit_list()
125 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y); in vmw_ldu_commit_list()
126 vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay); in vmw_ldu_commit_list()
127 vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay); in vmw_ldu_commit_list()
A Dvmwgfx_drv.c451 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); in vmw_device_init()
458 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); in vmw_device_init()
471 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); in vmw_device_fini()
477 vmw_write(vmw, SVGA_REG_CONFIG_DONE, in vmw_device_fini()
479 vmw_write(vmw, SVGA_REG_ENABLE, in vmw_device_fini()
481 vmw_write(vmw, SVGA_REG_TRACES, in vmw_device_fini()
807 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? in vmw_detect_version()
932 vmw_write(dev_priv, SVGA_REG_DEV_CAP, in vmw_driver_load()
936 vmw_write(dev_priv, SVGA_REG_DEV_CAP, in vmw_driver_load()
1348 vmw_write(dev_priv, SVGA_REG_ENABLE, in __vmw_svga_disable()
[all …]
A Dvmwgfx_irq.c239 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
250 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
297 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); in vmw_irq_uninstall()
A Dvmwgfx_kms.c140 vmw_write(dev_priv, SVGA_REG_CURSOR_X, x); in vmw_cursor_update_position()
141 vmw_write(dev_priv, SVGA_REG_CURSOR_Y, y); in vmw_cursor_update_position()
142 vmw_write(dev_priv, SVGA_REG_CURSOR_ON, show ? 1 : 0); in vmw_cursor_update_position()
1887 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch); in vmw_kms_write_svga()
1890 vmw_write(vmw_priv, SVGA_REG_WIDTH, width); in vmw_kms_write_svga()
1891 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height); in vmw_kms_write_svga()
1893 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp); in vmw_kms_write_svga()
2029 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8); in vmw_du_crtc_gamma_set()
2030 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8); in vmw_du_crtc_gamma_set()
2031 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8); in vmw_du_crtc_gamma_set()
A Dvmwgfx_devcaps.c95 vmw_write(vmw, SVGA_REG_DEV_CAP, i); in vmw_devcaps_create()
A Dvmwgfx_cmd.c137 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); in vmw_fifo_create()
155 vmw_write(dev_priv, SVGA_REG_SYNC, reason); in vmw_fifo_ping_host()
A Dvmwgfx_cmdbuf.c308 vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val); in vmw_cmdbuf_header_submit()
312 vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val); in vmw_cmdbuf_header_submit()
A Dvmwgfx_drv.h678 static inline void vmw_write(struct vmw_private *dev_priv, in vmw_write() function
1678 vmw_write(vmw, SVGA_REG_IRQ_STATUS, status); in vmw_irq_status_write()

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