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Searched refs:vpu (Results 1 – 25 of 109) sorted by relevance

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/linux/drivers/media/platform/mtk-vpu/
A Dmtk_vpu.c278 vpu_running(vpu), vpu_cfg_readl(vpu, VPU_PC_REG), in vpu_dump_status()
279 vpu_cfg_readl(vpu, VPU_RA_REG), vpu_cfg_readl(vpu, VPU_SP_REG), in vpu_dump_status()
294 if (!vpu) { in vpu_ipi_register()
419 if (!vpu) { in vpu_wdt_reg_handler()
575 run = &vpu->run; in vpu_load_firmware()
642 strscpy(vpu->run.fw_ver, run->fw_ver, sizeof(vpu->run.fw_ver)); in vpu_init_ipi_handler()
767 vpu->recv_buf = vpu->reg.tcm + VPU_DTCM_OFFSET; in vpu_ipi_init()
768 vpu->send_buf = vpu->recv_buf + 1; in vpu_ipi_init()
796 queue_work(vpu->wdt.wq, &vpu->wdt.ws); in vpu_irq_handler()
819 vpu = devm_kzalloc(dev, sizeof(*vpu), GFP_KERNEL); in mtk_vpu_probe()
[all …]
/linux/drivers/media/platform/mtk-vcodec/
A Dvdec_vpu_if.c22 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
26 mtk_vcodec_debug(vpu, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
42 mtk_vcodec_debug(vpu, "firmware version 0x%x\n", vpu->fw_abi_version); in handle_init_ack_msg()
52 vpu->failure = 1; in handle_init_ack_msg()
76 vpu->signaled = 1; in vpu_dec_ipi_handler()
105 vpu->failure = 0; in vcodec_vpu_send_msg()
106 vpu->signaled = 0; in vcodec_vpu_send_msg()
108 err = mtk_vcodec_fw_ipi_send(vpu->ctx->dev->fw_handler, vpu->id, msg, in vcodec_vpu_send_msg()
116 return vpu->failure; in vcodec_vpu_send_msg()
148 err = mtk_vcodec_fw_ipi_register(vpu->ctx->dev->fw_handler, vpu->id, in vpu_dec_init()
[all …]
A Dvenc_vpu_if.c17 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_enc_init_msg()
33 vpu->failure = 1; in handle_enc_init_msg()
56 vpu->signaled = 1; in vpu_enc_ipi_handler()
58 if (vpu->failure) in vpu_enc_ipi_handler()
93 status = mtk_vcodec_fw_ipi_send(vpu->ctx->dev->fw_handler, vpu->id, msg, in vpu_enc_send_msg()
100 if (vpu->failure) in vpu_enc_send_msg()
116 vpu->signaled = 0; in vpu_enc_init()
117 vpu->failure = 0; in vpu_enc_init()
119 status = mtk_vcodec_fw_ipi_register(vpu->ctx->dev->fw_handler, vpu->id, in vpu_enc_init()
215 mtk_vcodec_err(vpu, in vpu_enc_set_param()
[all …]
/linux/drivers/staging/media/hantro/
A Dhantro_g2_hevc_dec.c22 vdpu_write(vpu, addr & 0xffffffff, offset); in hantro_write_addr()
27 struct hantro_dev *vpu = ctx->dev; in prepare_tile_info_buffer() local
126 struct hantro_dev *vpu = ctx->dev; in set_params() local
184 hantro_reg_write(vpu, &g2_sao_e, in set_params()
228 hantro_reg_write(vpu, &g2_pcm_e, in set_params()
287 struct hantro_dev *vpu = ctx->dev; in set_ref_pic_list() local
370 struct hantro_dev *vpu = ctx->dev; in set_ref() local
487 struct hantro_dev *vpu = ctx->dev; in set_buffers() local
521 struct hantro_dev *vpu = ctx->dev; in prepare_scaling_list_buffer() local
588 struct hantro_dev *vpu = ctx->dev; in hantro_g2_hevc_dec_run() local
[all …]
A Dhantro_drv.c87 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
855 vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL); in hantro_probe()
856 if (!vpu) in hantro_probe()
876 vpu->clocks[i].id = vpu->variant->clk_names[i]; in hantro_probe()
907 vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; in hantro_probe()
908 vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; in hantro_probe()
940 dev_name(vpu->dev), vpu); in hantro_probe()
949 ret = vpu->variant->init(vpu); in hantro_probe()
980 vpu->mdev.dev = vpu->dev; in hantro_probe()
986 vpu->v4l2_dev.mdev = &vpu->mdev; in hantro_probe()
[all …]
A Dimx8m_vpu_hw.c58 ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks); in imx8mq_runtime_resume()
72 clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); in imx8mq_runtime_resume()
156 struct hantro_dev *vpu = dev_id; in imx8m_vpu_g1_irq() local
167 hantro_irq_done(vpu, state); in imx8m_vpu_g1_irq()
174 struct hantro_dev *vpu = dev_id; in imx8m_vpu_g2_irq() local
185 hantro_irq_done(vpu, state); in imx8m_vpu_g2_irq()
192 vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; in imx8mq_vpu_hw_init()
199 struct hantro_dev *vpu = ctx->dev; in imx8m_vpu_g1_reset() local
201 imx8m_soft_reset(vpu, RESET_G1); in imx8m_vpu_g1_reset()
206 struct hantro_dev *vpu = ctx->dev; in imx8m_vpu_g2_reset() local
[all …]
A Dhantro_postproc.c17 hantro_reg_write(vpu, \
24 hantro_reg_write_s(vpu, \
56 struct hantro_dev *vpu = ctx->dev; in hantro_needs_postproc() local
61 if (!vpu->variant->postproc_fmts) in hantro_needs_postproc()
69 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_enable() local
74 if (!vpu->variant->postproc_regs) in hantro_postproc_enable()
96 HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1); in hantro_postproc_enable()
113 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_free() local
129 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_alloc() local
158 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_disable() local
[all …]
A Drockchip_vpu2_hw_jpeg_enc.c46 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
59 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
71 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in rockchip_vpu2_jpeg_enc_set_buffers()
95 rockchip_vpu2_jpeg_enc_set_qtable(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_qtable() argument
123 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu2_jpeg_enc_run() local
141 vepu_write_relaxed(vpu, VEPU_REG_ENCODE_FORMAT_JPEG, in rockchip_vpu2_jpeg_enc_run()
144 rockchip_vpu2_set_src_img_ctrl(vpu, ctx); in rockchip_vpu2_jpeg_enc_run()
146 rockchip_vpu2_jpeg_enc_set_qtable(vpu, in rockchip_vpu2_jpeg_enc_run()
157 vepu_write(vpu, reg, VEPU_REG_DATA_ENDIAN); in rockchip_vpu2_jpeg_enc_run()
160 vepu_write_relaxed(vpu, reg, VEPU_REG_AXI_CTRL); in rockchip_vpu2_jpeg_enc_run()
[all …]
A Drockchip_vpu2_hw_vp8_dec.c280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
333 hantro_reg_write(vpu, &vp8_dec_quant[i], in cfg_qp()
347 struct hantro_dev *vpu = ctx->dev; in cfg_parts() local
430 struct hantro_dev *vpu = ctx->dev; in cfg_tap() local
439 hantro_reg_write(vpu, in cfg_tap()
450 struct hantro_dev *vpu = ctx->dev; in cfg_ref() local
487 struct hantro_dev *vpu = ctx->dev; in cfg_buffers() local
[all …]
A Dhantro_h1_jpeg_enc.c28 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
40 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in hantro_h1_jpeg_enc_set_buffers()
42 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size, in hantro_h1_jpeg_enc_set_buffers()
65 hantro_h1_jpeg_enc_set_qtable(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_qtable() argument
93 struct hantro_dev *vpu = ctx->dev; in hantro_h1_jpeg_enc_run() local
111 vepu_write_relaxed(vpu, H1_REG_ENC_CTRL_ENC_MODE_JPEG, in hantro_h1_jpeg_enc_run()
114 hantro_h1_set_src_img_ctrl(vpu, ctx); in hantro_h1_jpeg_enc_run()
116 hantro_h1_jpeg_enc_set_qtable(vpu, in hantro_h1_jpeg_enc_run()
128 vepu_write(vpu, reg, H1_REG_AXI_CTRL); in hantro_h1_jpeg_enc_run()
138 vepu_write(vpu, reg, H1_REG_ENC_CTRL); in hantro_h1_jpeg_enc_run()
[all …]
A Dhantro_g1_vp8_dec.c139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
195 hantro_reg_write(vpu, &vp8_dec_quant[i], in cfg_qp()
234 struct hantro_dev *vpu = ctx->dev; in cfg_parts() local
282 hantro_reg_write(vpu, &reg, mb_size + 1); in cfg_parts()
306 vdpu_write_relaxed(vpu, in cfg_parts()
332 struct hantro_dev *vpu = ctx->dev; in cfg_tap() local
365 hantro_reg_write(vpu, &reg, val); in cfg_tap()
373 struct hantro_dev *vpu = ctx->dev; in cfg_ref() local
411 struct hantro_dev *vpu = ctx->dev; in cfg_buffers() local
[all …]
A Drockchip_vpu_hw.c208 struct hantro_dev *vpu = dev_id; in rockchip_vpu1_vepu_irq() local
217 vepu_write(vpu, 0, H1_REG_AXI_CTRL); in rockchip_vpu1_vepu_irq()
219 hantro_irq_done(vpu, state); in rockchip_vpu1_vepu_irq()
226 struct hantro_dev *vpu = dev_id; in rockchip_vpu2_vdpu_irq() local
237 hantro_irq_done(vpu, state); in rockchip_vpu2_vdpu_irq()
244 struct hantro_dev *vpu = dev_id; in rockchip_vpu2_vepu_irq() local
255 hantro_irq_done(vpu, state); in rockchip_vpu2_vepu_irq()
284 struct hantro_dev *vpu = ctx->dev; in rk3066_vpu_dec_reset() local
292 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu1_enc_reset() local
301 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu2_dec_reset() local
[all …]
A Dhantro_g1_h264_dec.c28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
113 vdpu_write_relaxed(vpu, in set_params()
130 struct hantro_dev *vpu = ctx->dev; in set_ref() local
209 struct hantro_dev *vpu = ctx->dev; in set_buffers() local
252 struct hantro_dev *vpu = ctx->dev; in hantro_g1_h264_dec_run() local
[all …]
A Drockchip_vpu2_hw_mpeg2_dec.c153 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu2_mpeg2_dec_run() local
173 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in rockchip_vpu2_mpeg2_dec_run()
177 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in rockchip_vpu2_mpeg2_dec_run()
182 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in rockchip_vpu2_mpeg2_dec_run()
185 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in rockchip_vpu2_mpeg2_dec_run()
193 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in rockchip_vpu2_mpeg2_dec_run()
199 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in rockchip_vpu2_mpeg2_dec_run()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_mpeg2_dec_run()
217 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120)); in rockchip_vpu2_mpeg2_dec_run()
225 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122)); in rockchip_vpu2_mpeg2_dec_run()
[all …]
A Drockchip_vpu2_hw_h264_dec.c199 struct hantro_dev *vpu = ctx->dev; in set_params() local
207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
302 struct hantro_dev *vpu = ctx->dev; in set_ref() local
426 struct hantro_dev *vpu = ctx->dev; in set_buffers() local
469 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu2_h264_dec_run() local
[all …]
A Dhantro_g1_mpeg2_dec.c111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
150 struct hantro_dev *vpu = ctx->dev; in hantro_g1_mpeg2_dec_run() local
181 vdpu_write_relaxed(vpu, reg, G1_SWREG(2)); in hantro_g1_mpeg2_dec_run()
194 vdpu_write_relaxed(vpu, reg, G1_SWREG(3)); in hantro_g1_mpeg2_dec_run()
200 vdpu_write_relaxed(vpu, reg, G1_SWREG(4)); in hantro_g1_mpeg2_dec_run()
208 vdpu_write_relaxed(vpu, reg, G1_SWREG(5)); in hantro_g1_mpeg2_dec_run()
212 vdpu_write_relaxed(vpu, reg, G1_SWREG(6)); in hantro_g1_mpeg2_dec_run()
221 vdpu_write_relaxed(vpu, reg, G1_SWREG(18)); in hantro_g1_mpeg2_dec_run()
225 vdpu_write_relaxed(vpu, reg, G1_SWREG(48)); in hantro_g1_mpeg2_dec_run()
228 vdpu_write_relaxed(vpu, reg, G1_SWREG(55)); in hantro_g1_mpeg2_dec_run()
[all …]
A Dhantro.h85 int (*init)(struct hantro_dev *vpu);
86 int (*runtime_resume)(struct hantro_dev *vpu);
339 writel_relaxed(val, vpu->enc_base + reg); in vepu_write_relaxed()
345 writel(val, vpu->enc_base + reg); in vepu_write()
350 u32 val = readl(vpu->enc_base + reg); in vepu_read()
360 writel_relaxed(val, vpu->dec_base + reg); in vdpu_write_relaxed()
366 writel(val, vpu->dec_base + reg); in vdpu_write()
371 u32 val = readl(vpu->dec_base + reg); in vdpu_read()
383 v = vdpu_read(vpu, reg->base); in vdpu_read_mask()
393 vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base); in hantro_reg_write()
[all …]
A Dhantro_g1.c16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
A Dhantro_hevc.c77 struct hantro_dev *vpu = ctx->dev; in hantro_hevc_ref_free() local
115 struct hantro_dev *vpu = ctx->dev; in hantro_hevc_get_ref_buf() local
124 dma_alloc_coherent(vpu->dev, in hantro_hevc_get_ref_buf()
163 struct hantro_dev *vpu = ctx->dev; in tile_buffer_reallocate() local
185 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
192 dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size, in tile_buffer_reallocate()
234 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
240 dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size, in tile_buffer_reallocate()
285 struct hantro_dev *vpu = ctx->dev; in hantro_hevc_dec_exit() local
307 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in hantro_hevc_dec_exit()
[all …]
/linux/drivers/remoteproc/
A Dingenic_rproc.c61 struct vpu { struct
71 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() argument
75 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
84 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
86 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
93 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
107 struct vpu *vpu = rproc->priv; in ingenic_rproc_stop() local
119 struct vpu *vpu = rproc->priv; in ingenic_rproc_kick() local
126 struct vpu *vpu = rproc->priv; in ingenic_rproc_da_to_va() local
155 struct vpu *vpu = rproc->priv; in vpu_interrupt() local
[all …]
/linux/drivers/media/platform/mtk-mdp/
A Dmtk_mdp_vpu.c15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
48 ctx = vpu_to_ctx(vpu); in mtk_mdp_vpu_ipi_handler()
55 ctx = vpu_to_ctx(vpu); in mtk_mdp_vpu_ipi_handler()
57 msg_id, vpu->failure); in mtk_mdp_vpu_ipi_handler()
81 if (!vpu->pdev) { in mtk_mdp_vpu_send_msg()
104 msg.ap_inst = (unsigned long)vpu; in mtk_mdp_vpu_send_ap_ipi()
106 if (!err && vpu->failure) in mtk_mdp_vpu_send_ap_ipi()
[all …]
A Dmtk_mdp_regs.c51 struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer; in mtk_mdp_hw_set_input_addr()
61 struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer; in mtk_mdp_hw_set_output_addr()
71 struct mdp_config *config = &ctx->vpu.vsi->src_config; in mtk_mdp_hw_set_in_size()
92 struct mdp_config *config = &ctx->vpu.vsi->src_config; in mtk_mdp_hw_set_in_image_format()
93 struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer; in mtk_mdp_hw_set_in_image_format()
107 struct mdp_config *config = &ctx->vpu.vsi->dst_config; in mtk_mdp_hw_set_out_size()
123 struct mdp_config *config = &ctx->vpu.vsi->dst_config; in mtk_mdp_hw_set_out_image_format()
124 struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer; in mtk_mdp_hw_set_out_image_format()
136 struct mdp_config_misc *misc = &ctx->vpu.vsi->misc; in mtk_mdp_hw_set_rotation()
145 struct mdp_config_misc *misc = &ctx->vpu.vsi->misc; in mtk_mdp_hw_set_global_alpha()
/linux/Documentation/devicetree/bindings/media/
A Drockchip-vpu.yaml20 - rockchip,rk3036-vpu
21 - rockchip,rk3066-vpu
22 - rockchip,rk3288-vpu
23 - rockchip,rk3328-vpu
24 - rockchip,rk3399-vpu
25 - rockchip,px30-vpu
27 - const: rockchip,rk3188-vpu
28 - const: rockchip,rk3066-vpu
30 - const: rockchip,rk3228-vpu
31 - const: rockchip,rk3399-vpu
[all …]
/linux/Documentation/devicetree/bindings/display/
A Damlogic,meson-vpu.yaml5 $id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
63 - amlogic,meson-gxbb-vpu # GXBB (S905)
64 - amlogic,meson-gxl-vpu # GXL (S905X, S905D)
65 - amlogic,meson-gxm-vpu # GXM (S912)
66 - const: amlogic,meson-gx-vpu
68 - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
75 - const: vpu
114 vpu: vpu@d0100000 {
115 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
117 reg-names = "vpu", "hhi";
/linux/Documentation/devicetree/bindings/remoteproc/
A Dingenic,vpu.yaml4 $id: "http://devicetree.org/schemas/remoteproc/ingenic,vpu.yaml#"
20 const: ingenic,jz4770-vpu-rproc
39 - description: vpu clock
44 - const: vpu
63 vpu: video-decoder@132a0000 {
64 compatible = "ingenic,jz4770-vpu-rproc";
73 clock-names = "aux", "vpu";

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