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/optee_os/lib/libmbedtls/mbedtls/library/
A Dssl_cache.c49 mbedtls_mutex_init( &cache->mutex ); in mbedtls_ssl_cache_init()
67 cur = cache->chain; in mbedtls_ssl_cache_get()
76 if( cache->timeout != 0 && in mbedtls_ssl_cache_get()
154 cur = cache->chain; in mbedtls_ssl_cache_set()
162 if( cache->timeout != 0 && in mbedtls_ssl_cache_set()
214 cur = cache->chain; in mbedtls_ssl_cache_set()
233 cache->chain = cur; in mbedtls_ssl_cache_set()
307 cache->timeout = timeout; in mbedtls_ssl_cache_set_timeout()
315 cache->max_entries = max; in mbedtls_ssl_cache_set_max_entries()
322 cur = cache->chain; in mbedtls_ssl_cache_free()
[all …]
/optee_os/core/arch/arm/dts/
A Dfsl-lx2160a.dtsi35 d-cache-sets = <128>;
38 i-cache-sets = <192>;
52 d-cache-sets = <128>;
55 i-cache-sets = <192>;
69 d-cache-sets = <128>;
72 i-cache-sets = <192>;
304 cache-level = <2>;
312 cache-level = <2>;
320 cache-level = <2>;
328 cache-level = <2>;
[all …]
A Dsama5d2.dtsi34 next-level-cache = <&L2>;
146 L2: cache-controller@a00000 {
147 compatible = "arm,pl310-cache";
150 cache-unified;
151 cache-level = <2>;
/optee_os/out/arm/export-ta_arm64/include/mbedtls/
A Dssl_cache.h96 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
126 void mbedtls_ssl_cache_set_timeout( mbedtls_ssl_cache_context *cache, int timeout );
136 void mbedtls_ssl_cache_set_max_entries( mbedtls_ssl_cache_context *cache, int max );
143 void mbedtls_ssl_cache_free( mbedtls_ssl_cache_context *cache );
/optee_os/out/arm/export-ta_arm32/host_include/mbedtls/
A Dssl_cache.h96 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
126 void mbedtls_ssl_cache_set_timeout( mbedtls_ssl_cache_context *cache, int timeout );
136 void mbedtls_ssl_cache_set_max_entries( mbedtls_ssl_cache_context *cache, int max );
143 void mbedtls_ssl_cache_free( mbedtls_ssl_cache_context *cache );
/optee_os/lib/libmbedtls/mbedtls/include/mbedtls/
A Dssl_cache.h96 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
126 void mbedtls_ssl_cache_set_timeout( mbedtls_ssl_cache_context *cache, int timeout );
136 void mbedtls_ssl_cache_set_max_entries( mbedtls_ssl_cache_context *cache, int max );
143 void mbedtls_ssl_cache_free( mbedtls_ssl_cache_context *cache );
/optee_os/out/arm/export-ta_arm32/include/mbedtls/
A Dssl_cache.h96 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
126 void mbedtls_ssl_cache_set_timeout( mbedtls_ssl_cache_context *cache, int timeout );
136 void mbedtls_ssl_cache_set_max_entries( mbedtls_ssl_cache_context *cache, int max );
143 void mbedtls_ssl_cache_free( mbedtls_ssl_cache_context *cache );
/optee_os/out/arm/export-ta_arm64/host_include/mbedtls/
A Dssl_cache.h96 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
126 void mbedtls_ssl_cache_set_timeout( mbedtls_ssl_cache_context *cache, int timeout );
136 void mbedtls_ssl_cache_set_max_entries( mbedtls_ssl_cache_context *cache, int max );
143 void mbedtls_ssl_cache_free( mbedtls_ssl_cache_context *cache );
/optee_os/out/arm/core/arch/arm/tee/
A D.cache.o.cmd1 …cache.o := /usr/bin/ccache /home/test/workspace/code/optee_3.16/build/../toolchains/aarch64/bin/aa…
A D.cache.o.d1 out/arm/core/arch/arm/tee/cache.o: core/arch/arm/tee/cache.c \
28 core/arch/arm/include/mm/generic_ram_layout.h core/include/tee/cache.h
/optee_os/core/arch/arm/kernel/
A Darm32_sysreg.txt70 DCCIMVAC c7 0 c14 1 WO Data cache clean and invalidate by MVA PoC
71 DCCISW c7 0 c14 2 WO Data cache clean and invalidate by set/way
72 DCCMVAC c7 0 c10 1 WO Data cache clean by MVA PoC
73 DCCMVAU c7 0 c11 1 WO Data cache clean by MVA PoU
74 DCCSW c7 0 c10 2 WO Data cache clean by set/way
75 DCIMVAC c7 0 c6 1 WO Data cache invalidate by MVA PoC
76 DCISW c7 0 c6 2 WO Data cache invalidate by set/way
77 ICIALLU c7 0 c5 0 WOD Instruction cache invalidate all PoU
78 ICIALLUIS c7 0 c1 0 WOD Instruction cache invalidate all PoU, IS
79 ICIMVAU c7 0 c5 1 WO Instruction cache invalidate by MVA PoU
A Dthread.c1633 struct thread_shm_cache *cache = &threads[thread_get_id()].shm_cache; in get_shm_cache_entry() local
1636 SLIST_FOREACH(ce, cache, link) in get_shm_cache_entry()
1643 SLIST_INSERT_HEAD(cache, ce, link); in get_shm_cache_entry()
1703 void thread_rpc_shm_cache_clear(struct thread_shm_cache *cache) in thread_rpc_shm_cache_clear() argument
1706 struct thread_shm_cache_entry *ce = SLIST_FIRST(cache); in thread_rpc_shm_cache_clear()
1710 SLIST_REMOVE_HEAD(cache, link); in thread_rpc_shm_cache_clear()
A Dthread_private.h248 void thread_rpc_shm_cache_clear(struct thread_shm_cache *cache);
/optee_os/
A D.azure-pipelines.yml53 displayName: 'Install SSH key for build cache'
55 hostname: 'cache.forissier.org'
56 …knownHostEntry: 'cache.forissier.org ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABgQDhjh94ShHh6M19+0NBjgX8Z…
58 sshKeySecureFile: 'ssh_rsa_build-cache'
71 …function download_cache() { ssh $SCP_OPT optee_os_ci@cache.forissier.org "cat ccache-$PROJ.tar.gz"…
72 … ! -e .uploaded ]; then echo Uploading cache && tar c -C $HOME .ccache | gzip -1 | ssh $SCP_OPT op…
A DCHANGELOG.md403 * pl310: fix cache sync ([#2035])
871 world, especially by adding a cache for FS RPC payload data.
872 - REE FS: use a single file per object, remove block cache.
/optee_os/core/arch/arm/tee/
A Dsub.mk11 srcs-y += cache.c
/optee_os/out/arm/core/include/generated/
A Darm32_sysreg.S385 # Data cache clean and invalidate by MVA PoC
390 # Data cache clean and invalidate by set/way
395 # Data cache clean by MVA PoC
400 # Data cache clean by MVA PoU
405 # Data cache clean by set/way
410 # Data cache invalidate by MVA PoC
415 # Data cache invalidate by set/way
420 # Instruction cache invalidate all PoU
426 # Instruction cache invalidate all PoU, IS
432 # Instruction cache invalidate by MVA PoU
/optee_os/core/arch/arm/plat-imx/pm/
A Dpsci-cpuidle-imx7.S736 mov r0, #0 @ ; write the cache size selection register to be
737 write_csselr r0 @ ; sure we address the data cache
746 write_dcisw r2 @ ; invalidate data or unified cache line by set/way
A Dpsci-suspend-imx7.S662 mov r0, #0 @ ; write the cache size selection register to be
663 write_csselr r0 @ ; sure we address the data cache
672 write_dcisw r2 @ ; invalidate data or unified cache line by set/way
/optee_os/out/arm/core/pta/tests/
A D.invoke.o.d31 lib/libutils/isoc/include/string.h core/include/tee/cache.h \
/optee_os/out/arm/core/
A D.tee.elf.cmd1 …ch_svc.o out/arm/core/arch/arm/tee/entry_fast.o out/arm/core/arch/arm/tee/cache.o out/arm/core/arc…
A Dtee.map2467 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2468 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2469 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2470 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2471 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2472 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2473 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2474 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2475 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
2476 .group 0x0000000000000000 0xc out/arm/core/arch/arm/tee/cache.o
[all …]
A Dtee.dmp545 0000000000000000 l df *ABS* 0000000000000000 cache.c
21699 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:19
21707 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:23
21710 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:24
21712 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:27
21719 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:57
21724 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:38
21728 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:57
21732 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:52
21734 /home/test/workspace/code/optee_3.16/optee_os/core/arch/arm/tee/cache.c:42
[all …]
/optee_os/lib/libmbedtls/mbedtls/
A DREADME.md147 CMake cache. This can be done with the following command using GNU find:
A DChangeLog181 * When using session cache based session resumption on the server,
182 double-check that custom session cache implementations return
533 fixes a local Lucky 13 cache attack found and reported by Tuba Yavuz,
1536 plaintext of messages under some conditions by using a cache attack
1547 previous entry) by using a cache attack targeting the SSL input record
2212 against side-channel attacks like the cache attack described in
2833 * Add countermeasure against "Lucky 13 strikes back" cache-based attack,
3432 * Add countermeasure against "Lucky 13 strikes back" cache-based attack,
3670 * The SSL session cache module (ssl_cache) now also retains peer_cert
3759 * Added simple SSL session cache implementation

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