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Searched refs:CTLR_ENABLE_G1NS_BIT (Results 1 – 3 of 3) sorted by relevance

/tf-a-ffa_el3_spmc/drivers/arm/gic/v3/
A Dgic600_multichip.c49 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in set_gicd_dchipr_rt_owner()
84 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in set_gicd_chipr_n()
205 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in gic600_multichip_init()
A Dgicv3_main.c204 CTLR_ENABLE_G1NS_BIT, in gicv3_distif_init()
837 CTLR_ENABLE_G1NS_BIT, in gicv3_distif_init_restore()
/tf-a-ffa_el3_spmc/include/drivers/arm/
A Dgicv3.h128 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT) macro

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