DAIF_FIQ_BIT (reference) in projects: tf-a-ffa_el3_spmc

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Searched refs:DAIF_FIQ_BIT (Results 1 – 13 of 13) sorted by relevance

/tf-a-ffa_el3_spmc/bl32/tsp/aarch64/
A D	tsp_entrypoint.S	`187 msr daifset, #DAIF_FIQ_BIT 464 msr daifclr, #DAIF_FIQ_BIT \| DAIF_IRQ_BIT 466 msr daifset, #DAIF_FIQ_BIT \| DAIF_IRQ_BIT`
/tf-a-ffa_el3_spmc/services/spd/opteed/
A D	opteed_common.c	`53 DAIF_FIQ_BIT \| in opteed_init_optee_ep_state()`
/tf-a-ffa_el3_spmc/plat/mediatek/common/
A D	mtk_plat_common.c	`116 daif = DAIF_ABT_BIT \| DAIF_IRQ_BIT \| DAIF_FIQ_BIT; in plat_get_spsr_for_bl33_entry()`
/tf-a-ffa_el3_spmc/drivers/renesas/common/watchdog/
A D	swdt.c	`141 write_daifset(DAIF_FIQ_BIT); in rcar_swdt_release()`
/tf-a-ffa_el3_spmc/plat/imx/common/
A D	imx_sip_handler.c	`243 (DAIF_FIQ_BIT \| DAIF_IRQ_BIT \| DAIF_ABT_BIT)); in imx_kernel_entry_handler()`
/tf-a-ffa_el3_spmc/include/arch/aarch64/
A D	arch_helpers.h	`310 write_daifclr(DAIF_FIQ_BIT); in enable_fiq() 338 write_daifset(DAIF_FIQ_BIT); in disable_fiq()`
A D	arch.h	`549 #define DAIF_FIQ_BIT (U(1) << 0) macro 589 (DAIF_FIQ_BIT \| DAIF_IRQ_BIT \| DAIF_ABT_BIT \| DAIF_DBG_BIT) 591 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT \| DAIF_IRQ_BIT)`
/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/
A D	bl31_plat_setup.c	`399 (DAIF_FIQ_BIT \| DAIF_IRQ_BIT \| DAIF_ABT_BIT)); in bl31_plat_get_next_kernel32_ep_info()`
/tf-a-ffa_el3_spmc/services/std_svc/spmd/
A D	spmd_main.c	`282 DAIF_FIQ_BIT \| in spmd_spmc_init()`
/tf-a-ffa_el3_spmc/services/spd/trusty/
A D	trusty.c	`469 DAIF_FIQ_BIT \| in trusty_setup()`
/tf-a-ffa_el3_spmc/lib/psci/
A D	psci_common.c	`677 daif = DAIF_ABT_BIT \| DAIF_IRQ_BIT \| DAIF_FIQ_BIT; in psci_get_ns_ep_info()`
/tf-a-ffa_el3_spmc/plat/renesas/rzg/
A D	bl2_plat_setup.c	`706 write_daifclr(DAIF_FIQ_BIT); in bl2_el3_early_platform_setup()`
/tf-a-ffa_el3_spmc/plat/renesas/rcar/
A D	bl2_plat_setup.c	`842 write_daifclr(DAIF_FIQ_BIT); in bl2_el3_early_platform_setup()`

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