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Searched refs:GIC_INTR_CFG_EDGE (Results 1 – 25 of 29) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/qti/common/src/
A Dqti_gic_v3.c24 GIC_INTR_CFG_EDGE),
27 GIC_INTR_CFG_EDGE),
30 GIC_INTR_CFG_EDGE),
36 GIC_INTR_CFG_EDGE),
39 GIC_INTR_CFG_EDGE),
42 GIC_INTR_CFG_EDGE),
45 GIC_INTR_CFG_EDGE),
48 GIC_INTR_CFG_EDGE),
51 GIC_INTR_CFG_EDGE),
55 GIC_INTR_CFG_EDGE),
[all …]
/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/include/
A Dplatform_def.h121 GIC_INTR_CFG_EDGE), \
123 GIC_INTR_CFG_EDGE), \
125 GIC_INTR_CFG_EDGE), \
127 GIC_INTR_CFG_EDGE), \
129 GIC_INTR_CFG_EDGE), \
131 GIC_INTR_CFG_EDGE), \
133 GIC_INTR_CFG_EDGE)
139 GIC_INTR_CFG_EDGE), \
141 GIC_INTR_CFG_EDGE), \
153 GIC_INTR_CFG_EDGE)
[all …]
/tf-a-ffa_el3_spmc/plat/socionext/synquacer/
A Dsq_gicv3.c24 GIC_INTR_CFG_EDGE),
27 GIC_INTR_CFG_EDGE),
36 GIC_INTR_CFG_EDGE),
39 GIC_INTR_CFG_EDGE),
42 GIC_INTR_CFG_EDGE),
45 GIC_INTR_CFG_EDGE),
48 GIC_INTR_CFG_EDGE),
51 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/arm/board/arm_fpga/include/
A Dplatform_def.h61 GIC_INTR_CFG_EDGE), \
63 GIC_INTR_CFG_EDGE), \
65 GIC_INTR_CFG_EDGE), \
67 GIC_INTR_CFG_EDGE), \
69 GIC_INTR_CFG_EDGE), \
71 GIC_INTR_CFG_EDGE)
75 GIC_INTR_CFG_EDGE), \
77 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/socionext/uniphier/
A Duniphier_gicv3.c24 GIC_INTR_CFG_EDGE),
27 GIC_INTR_CFG_EDGE),
36 GIC_INTR_CFG_EDGE),
39 GIC_INTR_CFG_EDGE),
42 GIC_INTR_CFG_EDGE),
45 GIC_INTR_CFG_EDGE),
48 GIC_INTR_CFG_EDGE),
51 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/include/
A Dplatform_def.h123 GIC_INTR_CFG_EDGE), \
125 GIC_INTR_CFG_EDGE), \
127 GIC_INTR_CFG_EDGE), \
129 GIC_INTR_CFG_EDGE), \
131 GIC_INTR_CFG_EDGE), \
133 GIC_INTR_CFG_EDGE), \
135 GIC_INTR_CFG_EDGE), \
137 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/ti/k3/include/
A Dplatform_def.h139 GIC_INTR_CFG_EDGE), \
141 GIC_INTR_CFG_EDGE), \
143 GIC_INTR_CFG_EDGE), \
145 GIC_INTR_CFG_EDGE), \
147 GIC_INTR_CFG_EDGE), \
149 GIC_INTR_CFG_EDGE)
153 GIC_INTR_CFG_EDGE), \
155 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/intel/soc/common/include/
A Dplatform_def.h199 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
201 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
203 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
205 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
207 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
209 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
211 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
213 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/st/stm32mp1/include/
A Dplatform_def.h157 grp, GIC_INTR_CFG_EDGE), \
160 grp, GIC_INTR_CFG_EDGE), \
163 grp, GIC_INTR_CFG_EDGE), \
166 grp, GIC_INTR_CFG_EDGE), \
169 grp, GIC_INTR_CFG_EDGE), \
172 grp, GIC_INTR_CFG_EDGE)
177 grp, GIC_INTR_CFG_EDGE), \
180 grp, GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/qemu/qemu/include/
A Dplatform_def.h244 grp, GIC_INTR_CFG_EDGE), \
246 grp, GIC_INTR_CFG_EDGE), \
248 grp, GIC_INTR_CFG_EDGE), \
250 grp, GIC_INTR_CFG_EDGE), \
252 grp, GIC_INTR_CFG_EDGE), \
254 grp, GIC_INTR_CFG_EDGE), \
256 grp, GIC_INTR_CFG_EDGE), \
258 grp, GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2162aqds/
A Dplat_def.h93 GIC_INTR_CFG_EDGE)
100 GIC_INTR_CFG_EDGE), \
102 GIC_INTR_CFG_EDGE), \
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2160aqds/
A Dplat_def.h93 GIC_INTR_CFG_EDGE)
100 GIC_INTR_CFG_EDGE), \
102 GIC_INTR_CFG_EDGE), \
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2160ardb/
A Dplat_def.h93 GIC_INTR_CFG_EDGE)
100 GIC_INTR_CFG_EDGE), \
102 GIC_INTR_CFG_EDGE), \
/tf-a-ffa_el3_spmc/plat/qemu/qemu_sbsa/include/
A Dplatform_def.h238 grp, GIC_INTR_CFG_EDGE), \
240 grp, GIC_INTR_CFG_EDGE), \
242 grp, GIC_INTR_CFG_EDGE), \
244 grp, GIC_INTR_CFG_EDGE), \
246 grp, GIC_INTR_CFG_EDGE), \
248 grp, GIC_INTR_CFG_EDGE), \
250 grp, GIC_INTR_CFG_EDGE), \
252 grp, GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/include/
A Dplatform_def.h135 GIC_INTR_CFG_EDGE), \
137 GIC_INTR_CFG_EDGE), \
139 GIC_INTR_CFG_EDGE), \
141 GIC_INTR_CFG_EDGE), \
143 GIC_INTR_CFG_EDGE), \
145 GIC_INTR_CFG_EDGE), \
147 GIC_INTR_CFG_EDGE), \
149 GIC_INTR_CFG_EDGE)) \
/tf-a-ffa_el3_spmc/plat/arm/board/corstone700/common/include/
A Dplatform_def.h252 (grp), GIC_INTR_CFG_EDGE), \
254 (grp), GIC_INTR_CFG_EDGE), \
256 (grp), GIC_INTR_CFG_EDGE), \
258 (grp), GIC_INTR_CFG_EDGE), \
260 (grp), GIC_INTR_CFG_EDGE), \
262 (grp), GIC_INTR_CFG_EDGE)
266 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/arm/board/a5ds/include/
A Dplatform_def.h65 GIC_INTR_CFG_EDGE), \
67 GIC_INTR_CFG_EDGE), \
69 GIC_INTR_CFG_EDGE), \
71 GIC_INTR_CFG_EDGE), \
73 GIC_INTR_CFG_EDGE), \
75 GIC_INTR_CFG_EDGE)
79 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/arm/board/fvp_ve/include/
A Dplatform_def.h74 GIC_INTR_CFG_EDGE), \
76 GIC_INTR_CFG_EDGE), \
78 GIC_INTR_CFG_EDGE), \
80 GIC_INTR_CFG_EDGE), \
82 GIC_INTR_CFG_EDGE), \
84 GIC_INTR_CFG_EDGE)
88 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/renesas/common/aarch64/
A Dplatform_common.c229 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
231 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
233 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
235 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
243 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
/tf-a-ffa_el3_spmc/plat/arm/board/diphda/common/include/
A Dplatform_def.h386 (grp), GIC_INTR_CFG_EDGE), \
388 (grp), GIC_INTR_CFG_EDGE), \
390 (grp), GIC_INTR_CFG_EDGE), \
392 (grp), GIC_INTR_CFG_EDGE), \
394 (grp), GIC_INTR_CFG_EDGE), \
396 (grp), GIC_INTR_CFG_EDGE)
400 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/include/plat/arm/common/
A Darm_def.h183 GIC_INTR_CFG_EDGE), \
185 GIC_INTR_CFG_EDGE), \
187 GIC_INTR_CFG_EDGE), \
189 GIC_INTR_CFG_EDGE), \
191 GIC_INTR_CFG_EDGE), \
193 GIC_INTR_CFG_EDGE)
197 GIC_INTR_CFG_EDGE), \
199 GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/include/
A Dplatform_def.h249 GIC_INTR_CFG_EDGE), \
251 GIC_INTR_CFG_EDGE)
255 GIC_INTR_CFG_EDGE), \
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A Dplat_setup.c192 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
194 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
196 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/
A Dplat_setup.c237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
/tf-a-ffa_el3_spmc/plat/xilinx/versal/include/
A Dplatform_def.h102 GIC_INTR_CFG_EDGE), \

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