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/tf-a-ffa_el3_spmc/fdts/
A Dfvp-ve-Cortex-A7x1.dts13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
34 #interrupt-cells = <3>;
35 #address-cells = <0>;
47 #clock-cells = <0>;
55 #address-cells = <2>;
56 #size-cells = <1>;
64 #interrupt-cells = <1>;
A Dstm32mp151.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
73 #size-cells = <1>;
[all …]
A Dfvp-ve-Cortex-A5x1.dts13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
55 #address-cells = <0>;
70 #clock-cells = <0>;
79 #clock-cells = <0>;
88 #clock-cells = <0>;
97 #clock-cells = <0>;
106 #clock-cells = <0>;
[all …]
A Dn1sdp.dtsi10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
72 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #size-cells = <2>;
94 #size-cells = <2>;
105 #msi-cells = <1>;
112 #msi-cells = <1>;
[all …]
A Dmorello.dtsi13 #address-cells = <2>;
14 #size-cells = <2>;
22 #address-cells = <2>;
23 #interrupt-cells = <3>;
24 #size-cells = <2>;
59 #mbox-cells = <2>;
69 #address-cells = <1>;
70 #size-cells = <1>;
86 #clock-cells = <0>;
93 #clock-cells = <0>;
A Dcorstone700.dtsi12 #address-cells = <1>;
13 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
37 #address-cells = <0>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
68 #clock-cells = <0>;
103 #size-cells = <1>;
121 #mbox-cells = <1>;
[all …]
A Dstm32mp157c-ev1.dts34 #address-cells = <1>;
35 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
53 #address-cells = <1>;
54 #size-cells = <1>;
A Dtc.dts12 #address-cells = <2>;
13 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
171 #size-cells = <2>;
190 #size-cells = <1>;
204 #mbox-cells = <2>;
216 #mbox-cells = <2>;
228 #size-cells = <0>;
245 #size-cells = <2>;
[all …]
A Dmorello-fvp.dts17 #address-cells = <2>;
18 #size-cells = <2>;
28 #address-cells = <2>;
29 #size-cells = <0>;
81 #address-cells = <2>;
82 #size-cells = <2>;
89 #address-cells = <2>;
90 #size-cells = <2>;
149 #size-cells = <0>;
153 #clock-cells = <1>;
[all …]
A Dfvp-foundation-gicv3-psci.dts26 #address-cells = <2>;
27 #size-cells = <2>;
50 #address-cells = <2>;
51 #size-cells = <0>;
92 #interrupt-cells = <3>;
93 #address-cells = <2>;
94 #size-cells = <2>;
128 #address-cells = <2>;
129 #size-cells = <2>;
149 #address-cells = <2>;
[all …]
A Dfvp-base-gicv3-psci-aarch32-common.dtsi18 #address-cells = <2>;
19 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
84 #interrupt-cells = <3>;
85 #address-cells = <2>;
86 #size-cells = <2>;
120 #address-cells = <2>;
121 #size-cells = <2>;
141 #address-cells = <2>;
[all …]
A Da5ds.dts13 #address-cells = <1>;
14 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
69 #clock-cells = <0>;
76 #clock-cells = <0>;
83 #clock-cells = <0>;
99 #interrupt-cells = <3>;
100 #address-cells = <0>;
127 #address-cells = <1>;
[all …]
A Dfvp-foundation-gicv2-psci.dts26 #address-cells = <2>;
27 #size-cells = <2>;
50 #address-cells = <2>;
51 #size-cells = <0>;
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
119 #address-cells = <2>;
120 #size-cells = <2>;
140 #address-cells = <2>;
141 #size-cells = <1>;
A Dfvp-base-gicv2-psci-aarch32.dts26 #address-cells = <2>;
27 #size-cells = <2>;
50 #address-cells = <1>;
51 #size-cells = <0>;
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
119 #address-cells = <2>;
120 #size-cells = <2>;
140 #address-cells = <2>;
141 #size-cells = <1>;
[all …]
A Dfvp-base-gicv2-psci.dts25 #address-cells = <2>;
26 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
91 #interrupt-cells = <3>;
92 #address-cells = <0>;
118 #address-cells = <2>;
119 #size-cells = <2>;
139 #address-cells = <2>;
140 #size-cells = <1>;
A Dfvp-base-gicv3-psci-common.dtsi24 #address-cells = <2>;
25 #size-cells = <2>;
102 #address-cells = <2>;
103 #size-cells = <0>;
144 #interrupt-cells = <3>;
145 #address-cells = <2>;
146 #size-cells = <2>;
180 #address-cells = <2>;
181 #size-cells = <2>;
201 #address-cells = <2>;
[all …]
A Darm_fpga.dts19 #address-cells = <2>;
20 #size-cells = <2>;
70 #clock-cells = <0>;
77 #clock-cells = <0>;
92 #address-cells = <2>;
93 #interrupt-cells = <3>;
94 #size-cells = <2>;
A Dfvp-foundation-motherboard.dtsi10 #address-cells = <2>; /* SMB chipselect number and offset */
11 #size-cells = <1>;
22 #clock-cells = <0>;
29 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #address-cells = <1>;
44 #size-cells = <1>;
51 #gpio-cells = <2>;
59 #clock-cells = <1>;
A Drtsm_ve-motherboard-aarch32.dtsi10 #address-cells = <2>; /* SMB chipselect number and offset */
11 #size-cells = <1>;
12 #interrupt-cells = <1>;
35 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #clock-cells = <0>;
56 #address-cells = <1>;
57 #size-cells = <1>;
64 #gpio-cells = <2>;
72 #clock-cells = <1>;
[all …]
A Dn1sdp-multi-chip.dts65 #iommu-cells = <1>;
75 #address-cells = <3>;
76 #size-cells = <2>;
81 #interrupt-cells = <1>;
103 #msi-cells = <1>;
110 #msi-cells = <1>;
A Drtsm_ve-motherboard.dtsi10 #address-cells = <2>; /* SMB chipselect number and offset */
11 #size-cells = <1>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #clock-cells = <0>;
55 #address-cells = <1>;
56 #size-cells = <1>;
63 #gpio-cells = <2>;
71 #clock-cells = <1>;
210 #clock-cells = <0>;
A Djuno-ethosn.dtsi8 #address-cells = <2>;
9 #size-cells = <2>;
/tf-a-ffa_el3_spmc/plat/arm/board/fvp/fdts/
A Dfvp_spmc_optee_sp_manifest.dts17 #address-cells = <2>;
18 #size-cells = <1>;
42 #address-cells = <0x2>;
43 #size-cells = <0x0>;
A Dfvp_spmc_manifest.dts17 #address-cells = <2>;
18 #size-cells = <1>;
63 #address-cells = <0x2>;
64 #size-cells = <0x0>;
/tf-a-ffa_el3_spmc/plat/arm/board/sgi575/fdts/
A Dsgi575_soc_fw_config.dts10 #address-cells = <2>;
11 #size-cells = <1>;

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