| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | psci-pd-tree.rst | 20 levels in the power domain tree to four.
23 mechanism used to populate the power domain topology tree.
36 #. The attributes of a core power domain differ from the attributes of power
39 performing a power management operation on the core power domain.
50 Describing a power domain tree
63 of power domains that are its direct children.
66 non-leaf power domains.
188 * CPU power domain i.e. non-leaf nodes.
204 /* Index of the parent power domain node */
213 /* Index of the parent power domain node */
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| A D | firmware-design.rst | 14 implementing power management use-cases (for example, secondary CPU boot,
569 - Initialize the power controller device.
720 the platform power management code with a Warm boot initialization
1100 the TSP to prepare for or respond to the power state change
1346 #. Processor specific power down sequences.
1410 CPU specific power down sequence
1415 retrieved during power down sequences.
1417 Various CPU drivers register handlers to perform power down at certain power
1419 request, determines the highest power level at which to execute power down
1429 turning off CCI coherency during a cluster power down.
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| A D | cpu-specific-build-macros.rst | 425 workaround results in increased DSU power consumption on idle.
431 increased DSU power consumption on idle.
440 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
443 is a known safe deviation from the Cortex-A57 TRM defined power down
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| /tf-a-ffa_el3_spmc/docs/perf/ |
| A D | psci-performance-juno.rst | 25 Juno supports CPU, cluster and system power down states, corresponding to power
67 power state to exiting the TF PSCI implementation. This corresponds to:
85 ``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
117 ``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
141 effectively serializes the SCP power down commands from all CPUs.
143 On platforms with a more efficient CPU power down mechanism, it should be
147 require locks at power level 0.
150 the cache associated with power level 0 is flushed (L1).
152 ``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
184 ``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
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| /tf-a-ffa_el3_spmc/docs/plat/ |
| A D | xilinx-zynqmp.rst | 56 The following power domain tree represents the power domain model used by TF-A
72 The 4 leaf power domains represent the individual A53 cores, while resources
73 common to the cluster are grouped in the power domain on the top.
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| A D | ls1043a.rst | 10 power supply and single clock design. The new 0.9V versions of the LS1043A
11 and LS1023A deliver addition power savings for applications such as Wireless
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| A D | nvidia-tegra.rst | 53 Denver also features new low latency power-state transitions, in addition
54 to extensive power-gating and dynamic voltage and clock scaling based on
138 The PSCI implementation expects each platform to expose the 'power state'
148 be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit.
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| A D | hikey.rst | 122 - Make sure Pin3-Pin4 on J15 are connected for recovery mode. Then power on HiKey.
151 - Make sure Pin3-Pin4 on J15 are open for normal boot mode. Then power on HiKey.
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| A D | imx8m.rst | 5 cores provide high-performance computing, power efficiency, enhanced system
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| A D | rcar-gen3.rst | 128 Trusted Environment with a modification to support power
134 plat-rcar: cpu-suspend: handle the power level
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| A D | hikey960.rst | 176 - Make sure "Boot Mode" switch is OFF for normal boot mode. Then power on HiKey960.
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| A D | rpi4.rst | 60 run after the SoC gets its power. The on-chip Boot ROM loads the next stage
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| A D | socionext-uniphier.rst | 94 still work without SCP, but SCP provides better power management support.
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| /tf-a-ffa_el3_spmc/docs/getting_started/ |
| A D | porting-guide.rst | 146 to know the highest power domain level that it should consider for power
153 Defines the local power state corresponding to the deepest power down
154 possible at every power domain level in the platform. The local power
157 value to initialize the local power states of the power domain nodes and
170 Defines the maximum number of local power states per power domain level
173 power domain level (power-down and retention). If the platform needs to
2136 level. Each entry contains the local power state the power domain at that power
2215 power states.
2219 of the power state i.e. for two power states X & Y, if X < Y
2333 target local power states for the CPU power domain and its parent
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| A D | psci-lib-integration-guide.rst | 34 do bookkeeping for the EL3 Runtime Software during power management.
68 whether the PSCI API resulted in power down of the CPU.
79 be preserved across CPU power down/power up cycles are maintained in
202 - Initializes PSCI power domain and state coordination data structures.
233 As explained in `Secure payload power management callback`_,
442 All platform specific operations for power management are done via
450 Secure payload power management callback
453 During PSCI power management operations, the EL3 Runtime Software may
462 appropriately during CPU power down/power up. Any secure interrupt targeted
464 to power down of the current CPU. During power up, these interrupt can be
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| /tf-a-ffa_el3_spmc/drivers/st/bsec/ |
| A D | bsec.c | 27 static uint32_t bsec_power_safmem(bool power);
198 result = bsec_power_safmem((bool)cfg->power & in bsec_set_config()
234 cfg->power = (uint8_t)((value & BSEC_CONF_POWER_UP_MASK) >> in bsec_get_config()
804 static uint32_t bsec_power_safmem(bool power) in bsec_power_safmem() argument
813 if (power) { in bsec_power_safmem()
822 if (power) { in bsec_power_safmem()
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| /tf-a-ffa_el3_spmc/plat/allwinner/common/ |
| A D | arisc_off.S | 32 # - Finally turn off the core's power switch by writing 0xff to the
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
74 l.sw 0x1540(r6), r5 # core power switch registers
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| /tf-a-ffa_el3_spmc/docs/about/ |
| A D | features.rst | 17 - Library support for CPU specific reset and power down sequences. This
25 - A generic |SCMI| driver to interface with conforming power controllers, for
31 - |PSCI| library support for CPU, cluster and system power management
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| /tf-a-ffa_el3_spmc/include/drivers/st/ |
| A D | bsec.h | 157 uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */ member
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| /tf-a-ffa_el3_spmc/docs/plat/arm/tc/ |
| A D | index.rst | 7 to abstract power and system management tasks away from application
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| /tf-a-ffa_el3_spmc/docs/plat/arm/ |
| A D | arm-build-options.rst | 44 for the construction of composite state-ID in the power-state parameter.
49 field of power-state parameter.
137 instead of SCPI/BOM driver for communicating with the SCP during power
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| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 169 - Added support for rtc power off sequence
244 early run-time power management
357 - Leave CPU power alone during BL31 setup
1132 improperly activated USB power rail
1348 - allwinner: power: Add DLDO4 power rail
3244 - Skip performing cache maintenance during power-up and power-down.
3253 (DSU). The power-down and power-up sequences are therefore mostly managed in
3264 allow platforms to power down the Redistributor during CPU power on/off.
3274 The SCMI driver implements the power domain management and system power
3487 requested at multiple power levels.
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| /tf-a-ffa_el3_spmc/fdts/ |
| A D | stm32mp157c-ed1.dts | 183 power-off-time-sec = <10>;
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| /tf-a-ffa_el3_spmc/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 7 this port ignores any power management features of the platform.
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| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | arm-sip-service.rst | 72 entered for the first time, following power on. This means CPU registers that
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