Searched refs:sdram_params (Results 1 – 2 of 2) sorted by relevance
193 if (sdram_params->dramtype == LPDDR4) in data_training()202 if (sdram_params->dramtype == LPDDR4) { in data_training()461 if (sdram_params->ch[i].col == 0) in dram_all_config()475 if (sdram_params->ch[i].rank == 1) in dram_all_config()479 DDR_STRIDE(sdram_params->stride); in dram_all_config()562 ch_count = sdram_params->num_channels; in dram_switch_to_next_index()703 phy_regs = &sdram_params->phy_regs; in dmc_suspend()820 pctl_cfg(channel, sdram_params); in dmc_resume()824 if (sdram_params->ch[channel].col) in dmc_resume()844 set_ddrconfig(sdram_params, channel, in dmc_resume()[all …]
181 struct rk3399_sdram_params *sdram_params, in sdram_timing_cfg_init() argument186 for (i = 0; i < sdram_params->num_channels; i++) { in sdram_timing_cfg_init()188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; in sdram_timing_cfg_init()189 for (j = 0; j < sdram_params->ch[i].rank; j++) { in sdram_timing_cfg_init()191 get_cs_die_capability(sdram_params, i, j); in sdram_timing_cfg_init()194 ptiming_config->dram_type = sdram_params->dramtype; in sdram_timing_cfg_init()195 ptiming_config->ch_cnt = sdram_params->num_channels; in sdram_timing_cfg_init()196 switch (sdram_params->dramtype) { in sdram_timing_cfg_init()
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