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Searched refs:win_id (Results 1 – 12 of 12) sorted by relevance

/tf-a-ffa_el3_spmc/drivers/marvell/
A Dccu.c76 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { in dump_ccu()
126 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { in ccu_enable_win()
148 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { in ccu_disable_win()
168 uint32_t win_id; in ccu_temp_win_insert() local
184 uint32_t win_id; in ccu_temp_win_remove() local
278 int win_id, idx; in ccu_save_win_range() local
280 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { in ccu_save_win_range()
293 int win_id, idx; in ccu_restore_win_range() local
295 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { in ccu_restore_win_range()
367 for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { in init_ccu()
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A Dio_win.c114 uint32_t win_id; in iow_temp_win_insert() local
130 uint32_t win_id; in iow_temp_win_remove() local
157 uint32_t trgt_id, win_id; in dump_io_win() local
164 for (win_id = 0; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++) { in dump_io_win()
170 win_id)); in dump_io_win()
186 int win_id, idx; in iow_save_win_range() local
189 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { in iow_save_win_range()
201 int win_id, idx; in iow_restore_win_range() local
204 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { in iow_restore_win_range()
250 for (win_id = 1; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++) in init_io_win()
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A Diob.c94 mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr); in iob_enable_win()
95 mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr); in iob_enable_win()
107 uint32_t win_id, win_cr, alr, ahr; in dump_iob() local
117 for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) { in dump_iob()
124 if (win_id != 0) { in dump_iob()
134 win_id, iob_target_name[target_id], in dump_iob()
165 uint32_t win_id, win_reg; in init_iob() local
187 for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) { in init_iob()
199 for (win_id = 1; win_id < win_count + 1; win_id++, win++) { in init_iob()
200 iob_win_check(win, win_id); in init_iob()
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A Damb_adec.c96 uint32_t ctrl, base, win_id, attr; in dump_amb_adec() local
102 for (win_id = 0; win_id < AMB_MAX_WIN_ID; win_id++) { in dump_amb_adec()
103 ctrl = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); in dump_amb_adec()
105 base = mmio_read_32(AMB_WIN_BASE_OFFSET(win_id)); in dump_amb_adec()
119 uint32_t win_id, win_reg; in init_amb_adec() local
138 for (win_id = 0; win_id < AMB_MAX_WIN_ID; win_id++) { in init_amb_adec()
139 win_reg = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); in init_amb_adec()
141 mmio_write_32(AMB_WIN_CR_OFFSET(win_id), win_reg); in init_amb_adec()
145 for (win_id = 0; win_id < win_count; win_id++, win++) { in init_amb_adec()
146 amb_check_win(win, win_id); in init_amb_adec()
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A Dgwin.c109 uint32_t win_id; in gwin_temp_win_insert() local
112 win_id = MVEBU_GWIN_MAX_WINS - i - 1; in gwin_temp_win_insert()
114 gwin_enable_window(ap_index, win, win_id); in gwin_temp_win_insert()
125 uint32_t win_id; in gwin_temp_win_remove() local
131 win_id = MVEBU_GWIN_MAX_WINS - i - 1; in gwin_temp_win_remove()
143 __func__, win_id); in gwin_temp_win_remove()
146 gwin_disable_window(ap_index, win_id); in gwin_temp_win_remove()
180 uint32_t win_id; in init_gwin() local
200 for (win_id = 0; win_id < MVEBU_GWIN_MAX_WINS; win_id++) in init_gwin()
201 gwin_disable_window(ap_index, win_id); in init_gwin()
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/tf-a-ffa_el3_spmc/drivers/marvell/mc_trustzone/
A Dmc_trustzone.c34 if ((win_id < 0) || (win_id > MVEBU_TZ_MAX_WINS)) { in tz_enable_win()
35 ERROR("Enabling wrong MC TrustZone window %d!\n", win_id); in tz_enable_win()
46 win_id); in tz_enable_win()
61 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), val); in tz_enable_win()
63 VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id, in tz_enable_win()
64 MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), in tz_enable_win()
65 mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id))); in tz_enable_win()
67 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), in tz_enable_win()
70 VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id, in tz_enable_win()
71 MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), in tz_enable_win()
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A Dmc_trustzone.h25 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id);
/tf-a-ffa_el3_spmc/plat/marvell/armada/a3k/common/
A Ddram_win.c187 int32_t win_id; in dram_win_map_build() local
192 for (win_id = 0; win_id < DRAM_WIN_MAP_NUM_MAX; win_id++) { in dram_win_map_build()
193 ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); in dram_win_map_build()
228 ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); in cpu_win_set()
230 mmio_write_32(CPU_DEC_WIN_CTRL_REG(win_id), ctrl_reg); in cpu_win_set()
241 mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); in cpu_win_set()
256 mmio_write_32(CPU_DEC_WIN_SIZE_REG(win_id), size_reg); in cpu_win_set()
262 mmio_write_32(CPU_DEC_WIN_CTRL_REG(win_id), ctrl_reg); in cpu_win_set()
267 uint32_t cfg_idx, win_id; in cpu_wins_init() local
277 for (win_id = 1; win_id < MV_CPU_WIN_NUM; win_id++) in cpu_wins_init()
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A Dio_addr_dec.c36 static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, in set_io_addr_dec_win() argument
56 win_id, dec_win->win_offset), in set_io_addr_dec_win()
59 if (win_id < dec_win->max_remap) in set_io_addr_dec_win()
61 win_id, dec_win->win_offset), base); in set_io_addr_dec_win()
64 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
68 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
71 win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, in set_io_addr_dec_win()
72 win_id, dec_win->win_offset)), in set_io_addr_dec_win()
74 win_id, dec_win->win_offset)), in set_io_addr_dec_win()
75 (win_id < dec_win->max_remap) ? in set_io_addr_dec_win()
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/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/mss/
A Dmss_bl2_setup.c52 int cfg_num, win_id, cfg_idx, cp; in bl2_plat_mmap_init() local
66 for (cfg_idx = 0, win_id = 1; in bl2_plat_mmap_init()
67 (win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) { in bl2_plat_mmap_init()
69 if (ccu_is_win_enabled(MVEBU_AP0, win_id)) in bl2_plat_mmap_init()
73 ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id); in bl2_plat_mmap_init()
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/
A Dplat_bl31_setup.c94 int tz_nr, win_id; in marvell_bl31_security_setup() local
98 for (win_id = 0; win_id < tz_nr; win_id++) in marvell_bl31_security_setup()
99 tz_enable_win(MVEBU_AP0, tz_map, win_id); in marvell_bl31_security_setup()
/tf-a-ffa_el3_spmc/include/drivers/marvell/
A Dccu.h42 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
49 int ccu_is_win_enabled(int ap_index, uint32_t win_id);

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