Searched refs:timing (Results 1 – 21 of 21) sorted by relevance

/trusted-firmware-a/drivers/st/fmc/
A D	stm32_fmc2_nand.c	172 timing = div_round_up(tar, hclkp) - 1U; in stm32_fmc2_nand_setup_timing() 176 timing = div_round_up(tclr, hclkp) - 1U; in stm32_fmc2_nand_setup_timing() 190 timing = div_round_up(twait, hclkp); in stm32_fmc2_nand_setup_timing() 191 tims.twait = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing() 207 timing = div_round_up(tset_mem, hclkp); in stm32_fmc2_nand_setup_timing() 208 tims.tset_mem = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing() 229 timing = div_round_up(thold_mem, hclkp); in stm32_fmc2_nand_setup_timing() 230 tims.thold_mem = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing() 252 timing = div_round_up(tset_att, hclkp); in stm32_fmc2_nand_setup_timing() 253 tims.tset_att = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing() [all …]
/trusted-firmware-a/fdts/
A D	stm32mp15-ddr.dtsi	39 st,ctl-timing = < 100 st,phy-timing = <
A D	tc.dts	337 panel-timing {
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/
A D	security-advisory-tfv-5.rst.txt	6 | | secure world timing information | 18 | Impact | Leakage of sensitive secure world timing information | 37 cause leakage of secure world timing information. This register should be added
A D	security-advisory-tfv-6.rst.txt	6 | | vulnerabilities using cache timing side-channels |
/trusted-firmware-a/docs/security_advisories/
A D	security-advisory-tfv-5.rst	6 | | secure world timing information | 18 | Impact | Leakage of sensitive secure world timing information | 37 cause leakage of secure world timing information. This register should be added
A D	security-advisory-tfv-6.rst	6 | | vulnerabilities using cache timing side-channels |
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/process/
A D	security-hardening.rst.txt	28 Preventing Secure-world timing information leakage via PMU counters 32 world from making it leak timing information. In general, higher privilege 44 Secure and Non-secure state. Thus, it attempts to leak timing information from 72 would allow it to carry out side-channel timing attacks against the Secure
A D	security.rst.txt	61 | | world timing information | 64 | | vulnerabilities using cache timing side-channels |
/trusted-firmware-a/docs/process/
A D	security-hardening.rst	28 Preventing Secure-world timing information leakage via PMU counters 32 world from making it leak timing information. In general, higher privilege 44 Secure and Non-secure state. Thus, it attempts to leak timing information from 72 would allow it to carry out side-channel timing attacks against the Secure
A D	security.rst	61 | | world timing information | 64 | | vulnerabilities using cache timing side-channels |
/trusted-firmware-a/drivers/st/ddr/
A D	stm32mp1_ram.c	191 CTL_PARAM(timing), in stm32mp1_ddr_setup() 195 PHY_PARAM(timing), in stm32mp1_ddr_setup()
/trusted-firmware-a/drivers/st/i2c/
A D	stm32_i2c.c	149 uint32_t timing = I2C_TIMING; in stm32_i2c_init() local 168 timing & TIMINGR_CLEAR_MASK); in stm32_i2c_init()
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/threat_model/
A D	threat_model_spm.rst.txt	557 | | Spectre, Meltdown or other cache timing |
A D	threat_model.rst.txt	742 | | side-channel timing attacks against TF-A. |
/trusted-firmware-a/docs/threat_model/
A D	threat_model_spm.rst	557 | | Spectre, Meltdown or other cache timing |
A D	threat_model.rst	742 | | side-channel timing attacks against TF-A. |
/trusted-firmware-a/docs/build/latex/
A D	trustedfirmware-a.aux	855 \@writefile{toc}{\contentsline {subsubsection}{Preventing Secure\sphinxhyphen {}world timing inform… 856 …:preventing-secure-world-timing-information-leakage-via-pmu-counters}{{3.9.1}{137}{Preventing Secu… 858 \newlabel{process/security-hardening:timing-leakage-attacks-from-the-non-secure-world}{{3.9.1}{137}…
A D	trustedfirmware-a.tex	10507 world timing information 10515 vulnerabilities using cache timing side\sphinxhyphen{}channels 12976 world from making it leak timing information. In general, higher privilege 13059 would allow it to carry out side\sphinxhyphen{}channel timing attacks against the Secure 23111 timing, the MPU hardware does not involve memory\sphinxhyphen{}resident translation tables. 45108 secure world timing information 45145 Leakage of sensitive secure world timing information 45182 cause leakage of secure world timing information. This register should be added 45215 vulnerabilities using cache timing side\sphinxhyphen{}channels 49157 side\sphinxhyphen{}channel timing attacks against TF\sphinxhyphen{}A. [all …]
/trusted-firmware-a/docs/components/
A D	xlat-tables-lib-v2-design.rst	115 timing, the MPU hardware does not involve memory-resident translation tables.
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/
A D	xlat-tables-lib-v2-design.rst.txt	115 timing, the MPU hardware does not involve memory-resident translation tables.

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