| /u-boot/scripts/kconfig/tests/auto_submenu/ |
| A D | Kconfig | 5 config A0 config
6 bool "A0"
14 depends on A0
17 This should be a submenu of A0.
24 This should line up with A0.
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| A D | expected_stdout | 2 A0 (A0) [Y/n/?] (NEW)
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| /u-boot/drivers/ddr/marvell/axp/ |
| A D | ddr3_axp_vars.h | 16 {"db_800-400", 0xA, 0x5, 0x0, A0, ddr3_A0_db_400, NULL},
17 {"db_1200-300", 0x2, 0xC, 0x0, A0, ddr3_A0_db_400, NULL},
18 {"db_1200-600", 0x2, 0x5, 0x0, A0, NULL, NULL},
19 {"db_1333-667", 0x3, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_667},
20 {"db_1600-800", 0xB, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_800},
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| A D | ddr3_hw_training.h | 301 A0, enumerator
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| A D | ddr3_init.c | 854 chip_board_rev = A0; in ddr3_get_static_ddr_mode()
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| /u-boot/board/maxbcm/ |
| A D | maxbcm.c | 80 {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL},
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| /u-boot/arch/arm/dts/ |
| A D | avnet-ultrazedev-som-v1.0.dtsi | 42 /* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
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| A D | stm32746g-eval-u-boot.dtsi | 144 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
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| A D | stm32f746-disco-u-boot.dtsi | 157 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
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| A D | stm32f769-disco-u-boot.dtsi | 194 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
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| A D | sama5d4.dtsi | 1902 … atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
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| /u-boot/board/Synology/ds414/ |
| A D | ds414.c | 103 {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
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| /u-boot/doc/device-tree-bindings/pinctrl/ |
| A D | kendryte,k210-fpioa.txt | 21 A0, A1, A2, B3, B4, B5, C6, C7
65 group = "A0";
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| /u-boot/board/theadorable/ |
| A D | theadorable.c | 107 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
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| /u-boot/lib/lzma/ |
| A D | LzmaDec.c | 25 #define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ argument
26 { UPDATE_0(p); i = (i + i); A0; } else \
55 #define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ argument
56 { UPDATE_0_CHECK; i = (i + i); A0; } else \
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| /u-boot/drivers/pinctrl/renesas/ |
| A D | pfc-r8a77970.c | 154 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
387 PINMUX_IPSR_GPSR(IP0_3_0, A0),
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| A D | pfc-r8a77980.c | 187 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F…
456 PINMUX_IPSR_GPSR(IP0_3_0, A0),
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| A D | pfc-r8a77990.c | 95 #define GPSR1_0 F_(A0, IP2_31_28)
222 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3…
638 PINMUX_IPSR_GPSR(IP2_31_28, A0),
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| A D | pfc-r8a77965.c | 92 #define GPSR1_0 F_(A0, IP1_31_28)
234 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_D…
701 PINMUX_IPSR_GPSR(IP1_31_28, A0),
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| A D | pfc-r8a7795.c | 85 #define GPSR1_0 F_(A0, IP1_31_28)
227 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_D…
693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
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| A D | pfc-r8a7796.c | 91 #define GPSR1_0 F_(A0, IP1_31_28)
233 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_D…
698 PINMUX_IPSR_GPSR(IP1_31_28, A0),
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| A D | pfc-r8a7792.c | 366 PINMUX_SINGLE(A0),
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| A D | pfc-r8a7794.c | 783 PINMUX_IPSR_GPSR(IP1_23_22, A0),
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| /u-boot/arch/arm/mach-rmobile/ |
| A D | pfc-r8a7740.c | 2023 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
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| A D | pfc-sh73a0.c | 1655 GPIO_FN(A0), \
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