Searched refs:AT91_PMC_PLL_CTRL0 (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 208 pmc_update_bits(base, AT91_PMC_PLL_CTRL0, in sam9x60_frac_pll_enable()
232 pmc_update_bits(base, AT91_PMC_PLL_CTRL0, in sam9x60_frac_pll_disable()
262 pmc_read(base, AT91_PMC_PLL_CTRL0, &val); in sam9x60_div_pll_enable()
268 pmc_update_bits(base, AT91_PMC_PLL_CTRL0, in sam9x60_div_pll_enable()
292 pmc_update_bits(base, AT91_PMC_PLL_CTRL0, in sam9x60_div_pll_disable()
321 pmc_read(base, AT91_PMC_PLL_CTRL0, &val); in sam9x60_div_pll_set_rate()
327 pmc_update_bits(base, AT91_PMC_PLL_CTRL0, in sam9x60_div_pll_set_rate()
357 pmc_read(base, AT91_PMC_PLL_CTRL0, &val); in sam9x60_div_pll_get_rate()
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| /u-boot/include/linux/clk/ |
| A D | at91_pmc.h | 36 #define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */ macro
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