ATMEL_MPDDRC_TPR0_TRCD_OFFSET (reference) in projects: u-boot

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Searched refs:ATMEL_MPDDRC_TPR0_TRCD_OFFSET (Results 1 – 17 of 17) sorted by relevance

/u-boot/board/gardena/smart-gateway-at91sam/
A D	spl.c	`93 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/atmel/sama5d27_som1_ek/
A D	sama5d27_som1_ek.c	`121 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) \| in ddrc_conf()`
/u-boot/board/atmel/sama5d2_xplained/
A D	sama5d2_xplained.c	`122 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddrc_conf()`
/u-boot/board/atmel/sama5d3_xplained/
A D	sama5d3_xplained.c	`154 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/laird/wb45n/
A D	wb45n.c	`161 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/laird/wb50n/
A D	wb50n.c	`156 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/atmel/at91sam9x5ek/
A D	at91sam9x5ek.c	`167 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/atmel/sama5d27_wlsom1_ek/
A D	sama5d27_wlsom1_ek.c	`164 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) \| in ddrc_conf()`
/u-boot/board/atmel/sama5d4_xplained/
A D	sama5d4_xplained.c	`170 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/atmel/sama5d2_icp/
A D	sama5d2_icp.c	`157 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) \| in ddrc_conf()`
/u-boot/board/atmel/sama5d4ek/
A D	sama5d4ek.c	`155 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/arch/arm/mach-at91/include/mach/
A D	atmel_mpddrc.h	`125 #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 macro`
/u-boot/board/siemens/corvus/
A D	board.c	`151 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|/* 27.5 = 15 ns / in ddr2_conf()`
/u-boot/board/atmel/at91sam9m10g45ek/
A D	at91sam9m10g45ek.c	`110 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|/* 27.5 = 15 ns / in ddr2_conf()`
/u-boot/board/atmel/at91sam9n12ek/
A D	at91sam9n12ek.c	`253 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/atmel/sama5d3xek/
A D	sama5d3xek.c	`227 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \| in ddr2_conf()`
/u-boot/board/mini-box/picosam9g45/
A D	picosam9g45.c	`64 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|/* 27.5 = 15 ns / in ddr2_conf()`

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