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/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dtimer.c45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
A Dpll.c102 #define CPM_CPXPCR_XLOCK BIT(6)
122 #define CPM_USBPCR_POR BIT(22)
187 #define CPM_MSCCDR_CE BIT(29)
246 #define CPM_LCR_SCPUS BIT(27)
247 #define CPM_LCR_VPUS BIT(26)
248 #define CPM_LCR_GPUS BIT(25)
249 #define CPM_LCR_GPSS BIT(24)
319 #define CPM_OPCR_O1SE BIT(4)
324 #define CPM_RSR_P0R BIT(2)
325 #define CPM_RSR_WR BIT(1)
[all …]
/u-boot/arch/mips/mach-ath79/include/mach/
A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dreset_manager_arria10.h55 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
56 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
59 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
60 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
61 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
62 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
72 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
88 #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
89 #define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
105 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
[all …]
/u-boot/drivers/net/
A Dftgmac100.h74 #define FTGMAC100_INT_RPKT_BUF BIT(0)
75 #define FTGMAC100_INT_RPKT_FIFO BIT(1)
76 #define FTGMAC100_INT_NO_RXBUF BIT(2)
77 #define FTGMAC100_INT_RPKT_LOST BIT(3)
78 #define FTGMAC100_INT_XPKT_ETH BIT(4)
79 #define FTGMAC100_INT_XPKT_FIFO BIT(5)
80 #define FTGMAC100_INT_NO_NPTXBUF BIT(6)
82 #define FTGMAC100_INT_AHB_ERR BIT(8)
191 #define FTGMAC100_TXDES0_LTS BIT(28)
192 #define FTGMAC100_TXDES0_FTS BIT(29)
[all …]
A Dmtk_eth.h25 #define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
66 #define TX_WB_DDONE BIT(6)
67 #define RX_DMA_BUSY BIT(3)
68 #define RX_DMA_EN BIT(2)
70 #define TX_DMA_EN BIT(0)
81 #define STRP_CRC BIT(16)
133 #define MAC_MODE BIT(16)
137 #define BKOFF_EN BIT(9)
138 #define BACKPR_EN BIT(8)
143 #define FORCE_DPX BIT(1)
[all …]
/u-boot/arch/arm/include/asm/arch-aspeed/
A Dwdt_ast2600.h23 #define WDT_CTRL_2ND_BOOT BIT(7)
26 #define WDT_CTRL_CLK1MHZ BIT(4)
27 #define WDT_CTRL_RESET BIT(1)
28 #define WDT_CTRL_EN BIT(0)
31 #define WDT_RESET_MASK1_RVAS BIT(25)
43 #define WDT_RESET_MASK1_DP BIT(13)
44 #define WDT_RESET_MASK1_HAC BIT(12)
52 #define WDT_RESET_MASK1_SOC BIT(4)
53 #define WDT_RESET_MASK1_SLI BIT(3)
54 #define WDT_RESET_MASK1_AHB BIT(2)
[all …]
/u-boot/drivers/clk/sunxi/
A Dclk_h616.c16 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
17 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
18 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
20 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
23 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
27 [CLK_SPI0] = GATE(0x940, BIT(31)),
28 [CLK_SPI1] = GATE(0x944, BIT(31)),
30 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
[all …]
A Dclk_r40.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
25 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
44 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
45 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
46 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
[all …]
A Dclk_a31.c17 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
21 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
22 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
26 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
40 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
41 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
42 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
[all …]
A Dclk_h3.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
38 [CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
40 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
41 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
[all …]
A Dclk_a64.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
35 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
36 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
38 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[all …]
A Dclk_h6.c17 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
18 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
19 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
20 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
25 [CLK_SPI0] = GATE(0x940, BIT(31)),
26 [CLK_SPI1] = GATE(0x944, BIT(31)),
28 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
29 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
[all …]
A Dclk_a83t.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
34 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
35 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
37 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[all …]
A Dclk_a23.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
24 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
32 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
33 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
[all …]
/u-boot/drivers/sound/
A Dmax98090.h71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
160 #define M98090_DIGMIC4_MASK BIT(3)
164 #define M98090_DIGMIC3_MASK BIT(2)
168 #define M98090_DIGMICR_MASK BIT(1)
172 #define M98090_DIGMICL_MASK BIT(0)
202 #define M98090_RJ_MASK BIT(5)
205 #define M98090_WCI_MASK BIT(4)
208 #define M98090_BCI_MASK BIT(3)
211 #define M98090_DLY_MASK BIT(2)
[all …]
A Dmax98088.h164 #define M98088_VSEN BIT(6)
165 #define M98088_ZDEN BIT(5)
166 #define M98088_EQ2EN BIT(1)
167 #define M98088_EQ1EN BIT(0)
170 #define M98088_INAEN BIT(7)
171 #define M98088_INBEN BIT(6)
172 #define M98088_MBEN BIT(3)
173 #define M98088_ADLEN BIT(1)
174 #define M98088_ADREN BIT(0)
177 #define M98088_HPLEN BIT(7)
[all …]
/u-boot/drivers/usb/mtu3/
A Dmtu3_hw_regs.h96 #define MAC2_INTR BIT(4)
97 #define DMA_INTR BIT(3)
98 #define MAC3_INTR BIT(2)
99 #define QMU_INTR BIT(1)
100 #define BMU_INTR BIT(0)
109 #define EP0ISR BIT(0)
270 #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
347 #define LGO_U3 BIT(4)
348 #define LGO_U2 BIT(3)
349 #define LGO_U1 BIT(2)
[all …]
/u-boot/include/net/pfe_eth/pfe/cbus/
A Demac.h33 #define EMAC_IEVENT_HBERR BIT(31)
34 #define EMAC_IEVENT_BABR BIT(30)
35 #define EMAC_IEVENT_BABT BIT(29)
36 #define EMAC_IEVENT_GRA BIT(28)
37 #define EMAC_IEVENT_TXF BIT(27)
38 #define EMAC_IEVENT_TXB BIT(26)
39 #define EMAC_IEVENT_RXF BIT(25)
40 #define EMAC_IEVENT_RXB BIT(24)
41 #define EMAC_IEVENT_MII BIT(23)
42 #define EMAC_IEVENT_EBERR BIT(22)
[all …]
/u-boot/drivers/mmc/
A Dtmio-common.h14 #define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
15 #define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
26 #define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
36 #define TMIO_SD_INFO1_CMP BIT(2) /* data complete */
44 #define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
85 #define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */
93 #define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */
98 #define TMIO_SD_DMA_RST_RD BIT(9)
99 #define TMIO_SD_DMA_RST_WR BIT(8)
106 #define TMIO_SD_DMA_INFO2_ERR_RD BIT(17)
[all …]
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dlvds_rk3288.h14 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
15 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
16 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
17 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
18 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
19 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
20 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
21 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
24 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
25 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
[all …]
/u-boot/board/mikrotik/crs3xx-98dx3236/
A Dcrs3xx-98dx3236.c23 #define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \
24 | BIT(6) | BIT(12) | BIT(13) \
25 | BIT(16) | BIT(17) | BIT(20) \
26 | BIT(29) | BIT(30)))
28 #define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \
29 | BIT(6) | BIT(12) | BIT(13) \
30 | BIT(16) | BIT(17) | BIT(20) \
31 | BIT(29) | BIT(30))
/u-boot/drivers/phy/marvell/
A Dcomphy_a3700.h27 #define rb_pin_pu_iveref BIT(1)
30 #define rb_pin_pu_pll BIT(16)
31 #define rb_pin_pu_rx BIT(17)
32 #define rb_pin_pu_tx BIT(18)
33 #define rb_pin_tx_idle BIT(19)
146 #define gen2_tx_data_dly_mask (BIT(3) | BIT(4))
156 #define bf_soft_rst BIT(0)
180 #define rb_pu_otg BIT(4)
183 #define rb_cdp_en BIT(2)
184 #define rb_dcp_en BIT(3)
[all …]
/u-boot/board/alliedtelesis/SBx81LIFKW/
A Dsbx81lifkw.c33 #define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
34 BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
36 #define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7))
37 #define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27))
53 BIT(18) | BIT(10)
58 BIT(18) | BIT(10),
59 BIT(18) | BIT(10)
65 BIT(18) | BIT(10)
71 BIT(18) | BIT(10)
161 writel((BIT(0) | BIT(1) | BIT(2) | in board_init()
[all …]
/u-boot/board/Marvell/db-xc3-24g4xg/
A Ddb-xc3-24g4xg.c23 #define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
24 | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
26 #define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
27 | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))

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