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Searched refs:CFG_DDR2_CONFIG_VAL (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dddr.c156 #define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \ macro
197 ddr_config = CFG_DDR2_CONFIG_VAL; in qca956x_ddr_init()

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