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Searched refs:CLK_PERI_UART0_PD (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h145 #define CLK_PERI_UART0_PD 11 macro
A Dmt7622-clk.h144 #define CLK_PERI_UART0_PD 12 macro
/u-boot/arch/arm/dts/
A Dmt7629.dtsi178 <&pericfg CLK_PERI_UART0_PD>;
A Dmt7622.dtsi173 <&pericfg CLK_PERI_UART0_PD>;
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c436 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
A Dclk-mt7629.c483 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17),

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