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Searched refs:CLK_TOP_F10M_REF_SEL (Results 1 – 5 of 5) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h92 #define CLK_TOP_F10M_REF_SEL 78 macro
A Dmt7622-clk.h74 #define CLK_TOP_F10M_REF_SEL 61 macro
/u-boot/arch/arm/dts/
A Dmt7629.dtsi288 <&topckgen CLK_TOP_F10M_REF_SEL>,
311 <&topckgen CLK_TOP_F10M_REF_SEL>;
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c320 MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
389 GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
A Dclk-mt7629.c373 MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),

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