Searched refs:CLK_TOP_MSDC30_0_SEL (Results 1 – 7 of 7) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 99 #define CLK_TOP_MSDC30_0_SEL 85 macro
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| A D | mt7622-clk.h | 81 #define CLK_TOP_MSDC30_0_SEL 68 macro
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| A D | mt7623-clk.h | 112 #define CLK_TOP_MSDC30_0_SEL 98 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7622.c | 331 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
434 GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
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| A D | clk-mt7623.c | 525 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
662 GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
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| A D | clk-mt7629.c | 384 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
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| /u-boot/arch/arm/dts/ |
| A D | mt7623.dtsi | 231 <&topckgen CLK_TOP_MSDC30_0_SEL>;
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