Searched refs:CLK_TOP_MSDC30_1_SEL (Results 1 – 9 of 9) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt8512-clk.h | 78 #define CLK_TOP_MSDC30_1_SEL 67 macro
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| A D | mt7629-clk.h | 100 #define CLK_TOP_MSDC30_1_SEL 86 macro
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| A D | mt7622-clk.h | 82 #define CLK_TOP_MSDC30_1_SEL 69 macro
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| A D | mt7623-clk.h | 113 #define CLK_TOP_MSDC30_1_SEL 99 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7622.c | 332 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
435 GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
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| A D | clk-mt8512.c | 480 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents,
770 GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
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| A D | clk-mt7623.c | 527 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
663 GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
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| A D | clk-mt7629.c | 385 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15),
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| /u-boot/arch/arm/dts/ |
| A D | mt7623.dtsi | 241 <&topckgen CLK_TOP_MSDC30_1_SEL>;
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