Searched refs:CLK_TOP_MSDC50_0_SEL (Results 1 – 8 of 8) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt8512-clk.h | 76 #define CLK_TOP_MSDC50_0_SEL 65 macro
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| A D | mt7629-clk.h | 98 #define CLK_TOP_MSDC50_0_SEL 84 macro
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| A D | mt7622-clk.h | 80 #define CLK_TOP_MSDC50_0_SEL 67 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8512.c | 473 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
767 GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
768 GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
769 GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
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| A D | clk-mt7622.c | 328 MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
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| A D | clk-mt7629.c | 381 MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
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| /u-boot/arch/arm/dts/ |
| A D | mt8512.dtsi | 155 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
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| A D | mt7622.dtsi | 185 <&topckgen CLK_TOP_MSDC50_0_SEL>;
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Completed in 16 milliseconds