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Searched refs:CONFIG_SYS_BR0_PRELIM (Results 1 – 25 of 34) sorted by relevance

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/u-boot/arch/powerpc/cpu/mpc83xx/elbc/
A Delbc.h2 #define CONFIG_SYS_BR0_PRELIM (\ macro
172 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
/u-boot/arch/powerpc/cpu/mpc8xxx/
A Dfsl_lbc.c66 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) in init_early_memctl_regs()
67 set_lbc_br(0, CONFIG_SYS_BR0_PRELIM); in init_early_memctl_regs()
/u-boot/board/xes/xpedite520x/
A Dxpedite520x.c40 set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); in flash_cs_fixup()
/u-boot/board/xes/xpedite537x/
A Dxpedite537x.c38 set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); in flash_cs_fixup()
/u-boot/board/xes/xpedite550x/
A Dxpedite550x.c38 set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); in flash_cs_fixup()
/u-boot/board/xes/xpedite517x/
A Dxpedite517x.c44 set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); in flash_cs_fixup()
/u-boot/include/configs/
A DP2041RDB.h199 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ macro
204 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ macro
210 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ macro
A Dsbc8548.h213 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M macro
222 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M macro
A Dcorenet_ds.h210 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ macro
215 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ macro
221 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ macro
A DM5272C3.h155 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 macro
A Dcobra5272.h261 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 macro
A Dsocrates.h103 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ macro
A DMPC8555CDS.h91 #define CONFIG_SYS_BR0_PRELIM 0xff801001 macro
A DMPC8541CDS.h93 #define CONFIG_SYS_BR0_PRELIM 0xff801001 macro
A DMPC8540ADS.h95 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ macro
A Dcontrolcenterd.h142 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ macro
A DMPC8568MDS.h99 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 macro
A DMPC8313ERDB_NAND.h202 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
A DMPC8560ADS.h96 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ macro
A Dxpedite520x.h107 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ macro
A DMPC8548CDS.h140 #define CONFIG_SYS_BR0_PRELIM \ macro
A Dp1_p2_rdb_pc.h371 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ macro
376 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ macro
/u-boot/arch/powerpc/cpu/mpc8xx/
A Dcpu_init.c139 out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM); in cpu_init_f()
/u-boot/configs/
A DMCR3000_defconfig20 CONFIG_SYS_BR0_PRELIM=0x04000801
/u-boot/board/socrates/
A Dsocrates.c92 (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); in misc_init_r()

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