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Searched refs:CONFIG_SYS_LBC_LCRR (Results 1 – 21 of 21) sorted by relevance

/u-boot/board/varisys/cyrus/
A Dcyrus.c68 out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR); in board_early_init_r()
/u-boot/include/configs/
A Dsocrates.h116 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ macro
A DMPC8555CDS.h150 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ macro
A DMPC8541CDS.h152 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ macro
A DMPC8540ADS.h154 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ macro
A DMPC8568MDS.h127 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ macro
A DMPC8560ADS.h155 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ macro
A Dsbc8548.h330 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ macro
A Dxpedite520x.h75 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) macro
A DMPC8548CDS.h211 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ macro
A Dxpedite550x.h93 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) macro
A Dxpedite537x.h91 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) macro
A Dkmp204x.h133 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) macro
A Dcyrus.h126 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) macro
A DP2041RDB.h118 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 macro
A Dxpedite517x.h99 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) macro
A Dcorenet_ds.h133 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 macro
/u-boot/board/socrates/
A Dsocrates.c150 uint lcrr = CONFIG_SYS_LBC_LCRR; in local_bus_init()
/u-boot/board/sbc8548/
A Dsbc8548.c64 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; in local_bus_init()
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dcpu_init.c729 #ifdef CONFIG_SYS_LBC_LCRR in cpu_init_r()
878 #ifdef CONFIG_SYS_LBC_LCRR in cpu_init_r()
883 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); in cpu_init_r()
/u-boot/scripts/
A Dconfig_whitelist.txt2803 CONFIG_SYS_LBC_LCRR

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