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Searched refs:CS0 (Results 1 – 25 of 93) sorted by relevance

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/u-boot/arch/arm/mach-omap2/omap3/
A Dsdrc.c42 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
57 size = get_sdr_cs_size(CS0); in make_cs1_contiguous()
172 write_sdrc_timings(CS0, sdrc_actim_base0, &timings); in do_sdrc_init()
186 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), in do_sdrc_init()
187 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); in do_sdrc_init()
190 timings.mr = readl(&sdrc_base->cs[CS0].mr); in do_sdrc_init()
203 size0 = get_sdr_cs_size(CS0); in dram_init()
224 size0 = get_sdr_cs_size(CS0); in dram_init_banksize()
243 do_sdrc_init(CS0, EARLY_INIT); in mem_init()
A Demif4.c43 if (cs == CS0) in get_sdr_cs_size()
133 size0 = get_sdr_cs_size(CS0); in dram_init()
150 size0 = get_sdr_cs_size(CS0); in dram_init_banksize()
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_pbs.c207 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
453 ddr3_pbs_write_pup_dqs_reg(CS0, in ddr3_tx_shift_dqs_adll_step_before_fail()
647 [dq], CS0, in ddr3_pbs_rx()
655 DQ_NUM, CS0, in ddr3_pbs_rx()
702 (PUP_DQS_RD, CS0, in ddr3_pbs_rx()
718 [dq], CS0, in ddr3_pbs_rx()
1047 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_rx_shift_dqs_to_first_fail()
1115 pbs_dq_mapping[idx][dq], CS0, in lock_pups()
1223 CS0, idx, 0, pbs_curr_val); in ddr3_pbs_per_bit()
1227 CS0, idx, 0, pbs_curr_val); in ddr3_pbs_per_bit()
[all …]
/u-boot/board/ccv/xpress/
A Dimximage.cfg160 DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
161 DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
162 DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
163 DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
165 device on CS0 */
/u-boot/doc/
A DREADME.fsl-ddr31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
37 | |CS0 Only| | | {CS0+CS1} | |
40 | |CS0 Only| | | {CS0+CS1} | |
43 | |CS0 Only| | | {CS0+CS1} | |
46 | | | | | {CS0+CS1} | |
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
408 DDR Chip-Select Interleaving Mode: CS0+CS1
/u-boot/arch/mips/dts/
A Dmscc,ocelot_pcb.dtsi34 reg = <0>; /* CS0 */
A Dservalt_pcb116.dts48 reg = <0>; /* CS0 */
A Dserval2_pcb112.dts49 reg = <0>; /* CS0 */
A Dserval_pcb105.dts49 reg = <0>; /* CS0 */
A Dserval_pcb106.dts49 reg = <0>; /* CS0 */
/u-boot/board/freescale/mpc837xemds/
A DREADME34 J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
55 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
/u-boot/board/sbc8548/
A DREADME127 have U-Boot in the 8MB flash, tied to /CS0.
129 If you are running the default 8MB /CS0 settings but want to store an
141 Finally, if you are running the alternate 64MB /CS0 settings and want
176 JP12 CS0/CS6 swap see note[*] see note[*]
191 onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
192 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
257 ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
/u-boot/board/freescale/mpc8315erdb/
A DREADME39 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
41 When booting from NAND, NAND flash is CS0 and NOR flash
/u-boot/board/Marvell/openrd/
A Dkwbimage.cfg123 # bit3-2: 00, CS0 hit selected
135 # bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
137 # bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
/u-boot/board/cloudengines/pogo_e02/
A Dkwbimage.cfg127 # bit3-2: 00, CS0 hit selected
139 # bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
141 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/u-boot/board/iomega/iconnect/
A Dkwbimage.cfg123 # bit3-2: 0x0, CS0 hit selected
135 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
137 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/u-boot/board/keymile/km_arm/
A Dkwbimage.cfg134 # bit3-2: 00, CS0 hit selected
143 # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
144 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/u-boot/board/raidsonic/ib62x0/
A Dkwbimage.cfg124 # bit3-2: 0x0, CS0 hit selected
136 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
138 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/u-boot/board/LaCie/net2big_v2/
A Dkwbimage.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/u-boot/board/LaCie/netspace_v2/
A Dkwbimage-is2.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
A Dkwbimage-ns2l.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
A Dkwbimage.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/u-boot/arch/arm/dts/
A Dam335x-draco.dtsi129 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
132 reg = <0 0 0>; /* CS0, offset 0 */
A Domap3-panel-sharp-ls037v7dw01.dtsi60 reg = <0>; /* CS0 */
/u-boot/board/freescale/mpc8313erdb/
A DREADME42 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
44 When booting from NAND, NAND flash is CS0 and NOR flash

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