Searched refs:DDRC_DBG1 (Results 1 – 6 of 6) sorted by relevance
| /u-boot/board/freescale/imx8mq_evk/ |
| A D | lpddr4_timing_b0.c | 16 { DDRC_DBG1(0), 0x00000001 },
115 { DDRC_DBG1(0), 0x00000000 },
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| A D | lpddr4_timing.c | 15 { DDRC_DBG1(0), 0x00000001 },
80 { DDRC_DBG1(0), 0x00000000 },
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| /u-boot/board/beacon/imx8mm/ |
| A D | lpddr4_timing.c | 13 { DDRC_DBG1(0), 0x00000001 },
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| /u-boot/board/freescale/imx8mm_evk/ |
| A D | lpddr4_timing.c | 13 { DDRC_DBG1(0), 0x00000001 },
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| /u-boot/drivers/ddr/imx/imx8m/ |
| A D | ddr_init.c | 141 reg32_write(DDRC_DBG1(0), 0x00000000); in ddr_init()
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | ddr.h | 480 #define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) macro
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