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Searched refs:DDRC_DDR_SS_GPR0 (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c148 reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ in ddr_init()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dimx-regs.h61 #define DDRC_DDR_SS_GPR0 0x3d000000 macro
A Dddr.h13 #define DDRC_DDR_SS_GPR0 0x3d000000 macro

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