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Searched refs:DDRC_FREQ1_DRAMTMG0 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c79 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c79 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c87 { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
A Dlpddr4_timing.c96 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h543 #define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) macro

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