Home
last modified time | relevance | path

Searched refs:DDRC_FREQ1_DRAMTMG1 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c80 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c80 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c88 { DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
A Dlpddr4_timing.c97 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h544 #define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) macro

Completed in 16 milliseconds