Home
last modified time | relevance | path

Searched refs:DDRC_FREQ1_DRAMTMG3 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c82 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c82 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c90 { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
A Dlpddr4_timing.c99 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h546 #define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) macro

Completed in 12 milliseconds