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Searched refs:DDRC_FREQ1_DRAMTMG5 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c84 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c84 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c92 { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
A Dlpddr4_timing.c101 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h548 #define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) macro

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