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Searched refs:DDRC_FREQ2_DRAMTMG3 (Results 1 – 4 of 4) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c103 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c103 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing.c120 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h579 #define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) macro

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