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Searched refs:DDRC_ODTCFG (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c105 { DDRC_ODTCFG(0), 0x0b060908 },
A Dlpddr4_timing.c70 { DDRC_ODTCFG(0), 0x0b060908 },
/u-boot/board/toradex/colibri_imx7/
A Dimximage.cfg105 /* DDRC_ODTCFG */
/u-boot/board/novtech/meerkat96/
A Dimximage.cfg92 DATA 4 0x307A0240 0x06000604 // DDRC_ODTCFG
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h464 #define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) macro

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