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Searched refs:DDRC_PERFLPR1 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c68 { DDRC_PERFLPR1(0), 0x900093e7 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c68 { DDRC_PERFLPR1(0), 0x900093e7 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c111 { DDRC_PERFLPR1(0), 0x90000096 },
A Dlpddr4_timing.c76 { DDRC_PERFLPR1(0), 0x90000096 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h469 #define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) macro

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