Searched refs:DDRC_PWRCTL (Results 1 – 7 of 7) sorted by relevance
| /u-boot/drivers/ddr/imx/imx8m/ |
| A D | ddr_init.c | 143 reg32_write(DDRC_PWRCTL(0), 0xa0); in ddr_init()
222 clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5)); in ddr_init()
246 setbits_le32(DDRC_PWRCTL(0), 0x1); in ddr_init()
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| /u-boot/arch/arm/mach-imx/mx7/ |
| A D | psci-mx7.c | 79 #define DDRC_PWRCTL 0x30 macro
529 writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
533 writel(0x20, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
536 writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x8, in imx_ddrc_enter_self_refresh()
537 DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
542 writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_exit_self_refresh()
545 writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x1, in imx_ddrc_exit_self_refresh()
546 DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_exit_self_refresh()
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| /u-boot/board/beacon/imx8mm/ |
| A D | lpddr4_timing.c | 14 { DDRC_PWRCTL(0), 0x00000001 },
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| /u-boot/board/freescale/imx8mm_evk/ |
| A D | lpddr4_timing.c | 14 { DDRC_PWRCTL(0), 0x00000001 },
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| /u-boot/board/freescale/imx8mq_evk/ |
| A D | lpddr4_timing_b0.c | 18 { DDRC_PWRCTL(0), 0x00000001 },
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| A D | lpddr4_timing.c | 16 { DDRC_PWRCTL(0), 0x00000001 },
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | ddr.h | 369 #define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) macro
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