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Searched refs:DDR_CTL_CONFIG_CPU_DDR_SYNC_SET (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dddr.c56 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) \ macro
148 #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

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