Home
last modified time | relevance | path

Searched refs:DDR_CTL_CONFIG_PAD_DDR2_SEL_SET (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dddr.c52 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) \ macro
204 ctl_config = CFG_DDR_CTL_CONFIG | DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1) | in qca956x_ddr_init()

Completed in 5 milliseconds