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Searched refs:HIT_INVALIDATE_D (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/mips/include/asm/
A Dcacheops.h59 #define HIT_INVALIDATE_D 0x11 macro
/u-boot/arch/mips/lib/
A Dcache.c175 cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); in invalidate_dcache_range()
/u-boot/arch/mips/mach-mtmips/
A Dddr_cal.c60 mips_cache(HIT_INVALIDATE_D, (u8 *)ca + i); in dqs_test_error()

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