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Searched refs:IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (Results 1 – 14 of 14) sorted by relevance

/u-boot/board/ge/bx50v3/
A Dbx50v3.c237 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display_b850v3()
278 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, in setup_display_bx50v3()
/u-boot/board/engicam/imx6q/
A Dimx6q.c183 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | in setup_display()
/u-boot/board/kosagi/novena/
A Dvideo.c426 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display_clock()
/u-boot/board/technexion/pico-imx6/
A Dpico-imx6.c287 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK in setup_display()
/u-boot/board/aristainetos/
A Daristainetos.c193 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) in enable_lvds()
/u-boot/board/ge/b1x5v2/
A Db1x5v2.c307 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, in setup_display()
/u-boot/board/embest/mx6boards/
A Dmx6boards.c500 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display()
/u-boot/board/advantech/dms-ba16/
A Ddms-ba16.c432 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display()
/u-boot/board/freescale/mx6sabreauto/
A Dmx6sabreauto.c479 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display()
/u-boot/board/toradex/apalis_imx6/
A Dapalis_imx6.c636 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK in setup_display()
/u-boot/board/toradex/colibri_imx6/
A Dcolibri_imx6.c543 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK in setup_display()
/u-boot/board/boundary/nitrogen6x/
A Dnitrogen6x.c750 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK in setup_display()
/u-boot/arch/arm/include/asm/arch-mx6/
A Dimx-regs.h567 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) macro
/u-boot/board/gateworks/gw_ventana/
A Dgw_ventana.c501 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) in setup_display()

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