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Searched refs:LPDDR4 (Results 1 – 18 of 18) sorted by relevance

/u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/
A Dfsp-m.txt124 0x3: 1x32 LPDDR4
287 /* DQA[0:7] pins of LPDDR4 module */
289 /* DQA[8:15] pins of LPDDR4 module */
291 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
297 /* DQA[0:7] pins of LPDDR4 module */
299 /* DQA[8:15] pins of LPDDR4 module */
301 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
308 /* DQA[0:7] pins of LPDDR4 module */
310 /* DQA[8:15] pins of LPDDR4 module */
319 /* DQA[0:7] pins of LPDDR4 module */
[all …]
/u-boot/drivers/ram/rockchip/
A DKconfig47 bool "LPDDR4 support for Rockchip RK3399"
50 This enables LPDDR4 sdram code support for the platforms based
A Dsdram_rk3399.c328 if (params->base.dramtype == LPDDR4) { in set_memory_map()
353 if (params->base.dramtype == LPDDR4) { in phy_io_config()
479 if (params->base.dramtype == LPDDR4) { in phy_io_config()
539 if (params->base.dramtype == LPDDR4) { in phy_io_config()
579 if (params->base.dramtype == LPDDR4) { in set_ds_odt()
661 if (params->base.dramtype == LPDDR4) in set_ds_odt()
883 if (params->base.dramtype == LPDDR4) in pctl_start()
983 if (params->base.dramtype == LPDDR4) in pctl_cfg()
1093 if (params->base.dramtype == LPDDR4) in data_training_ca()
1331 if (params->base.dramtype == LPDDR4) in data_training_wdql()
[all …]
A Dsdram_common.c29 case LPDDR4: in sdram_print_dram_type()
292 if (dram_type == DDR3 || dram_type == LPDDR4) { in sdram_detect_dbw()
A Dsdram-rk3399-lpddr4-400.inc78 .dramtype = LPDDR4,
A Dsdram-rk3399-lpddr4-800.inc78 .dramtype = LPDDR4,
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram.h14 LPDDR4 = 0x7, enumerator
/u-boot/arch/arm/mach-imx/imx8m/
A DKconfig41 bool "imx8mm LPDDR4 EVK board"
59 bool "imx8mp LPDDR4 EVK board"
/u-boot/drivers/ddr/imx/imx8m/
A DKconfig11 Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
/u-boot/arch/x86/dts/
A Dchromebook_coral.dts721 /* DQA[0:7] pins of LPDDR4 module */
723 /* DQA[8:15] pins of LPDDR4 module */
725 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
731 /* DQA[0:7] pins of LPDDR4 module */
733 /* DQA[8:15] pins of LPDDR4 module */
735 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
742 /* DQA[0:7] pins of LPDDR4 module */
744 /* DQA[8:15] pins of LPDDR4 module */
746 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
753 /* DQA[0:7] pins of LPDDR4 module */
[all …]
/u-boot/arch/arm/mach-mediatek/
A DKconfig53 and several LPDDR3 and LPDDR4 options.
/u-boot/doc/board/amlogic/
A Dbeelink-gtking.rst9 - 4GB LPDDR4 RAM
A Dbeelink-gtkingpro.rst9 - 4GB LPDDR4 RAM
A Dkhadas-vim3.rst10 - 4GB LPDDR4 SDRAM
A Dkhadas-vim3l.rst10 - 2GB LPDDR4 SDRAM
/u-boot/board/google/
A DKconfig16 LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB),
/u-boot/arch/arm/mach-rockchip/rk3399/
A DKconfig99 * 4GB Dual-Channel LPDDR4 64-bit
/u-boot/board/hisilicon/hikey960/
A DREADME8 * 3GB LPDDR4 SDRAM

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