Home
last modified time | relevance | path

Searched refs:OCTEON_DDR1_BASE (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-octeon/include/mach/
A Dcvmx-bootmem.h30 #define OCTEON_DDR1_BASE ((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) \ macro
/u-boot/arch/mips/mach-octeon/
A Dcvmx-bootmem.c1196 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); in cvmx_bootmem_phy_mem_list_init()
1200 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); in cvmx_bootmem_phy_mem_list_init()
1315 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE | in cvmx_bootmem_phy_mem_list_init_multi()
1322 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE | in cvmx_bootmem_phy_mem_list_init_multi()

Completed in 8 milliseconds