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Searched refs:POWER_AND_PLL_CTRL_REG (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-mvebu/serdes/a38x/
A Dhigh_speed_env_spec.c188 {POWER_AND_PLL_CTRL_REG, 0x800, 0x0e0, {0x0, 0x80}, 0, 0},
602 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x2}, 0, 0},
616 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x3}, 0, 0},
630 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x0}, 0, 0},
707 {POWER_AND_PLL_CTRL_REG, 0x800, 0xff, {0xfc81}, 0, 0},
2086 reg_data = reg_read(POWER_AND_PLL_CTRL_REG + in hws_ref_clock_set()
2090 reg_write(POWER_AND_PLL_CTRL_REG + in hws_ref_clock_set()
A Dsys_env_lib.h41 #define POWER_AND_PLL_CTRL_REG 0xa0004 macro

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