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Searched refs:REG_DRAM_TRAINING_AUTO_OFFS (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_write_leveling.c92 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw()
98 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw()
227 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_wl_supplement()
515 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw_reg_dimm()
521 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw_reg_dimm()
A Dddr3_axp.h222 #define REG_DRAM_TRAINING_AUTO_OFFS 31 macro
A Dddr3_read_leveling.c80 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_read_leveling_hw()
86 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_read_leveling_hw()
198 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_read_leveling_sw()
A Dddr3_hw_training.c633 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_load_patterns()
674 reg |= (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_load_patterns()
A Dddr3_dqs.c147 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_dqs_centralization_rx()
229 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_dqs_centralization_tx()
A Dddr3_pbs.c116 reg = 1 << REG_DRAM_TRAINING_AUTO_OFFS; in ddr3_pbs_tx()
559 reg = 1 << REG_DRAM_TRAINING_AUTO_OFFS; in ddr3_pbs_rx()

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